 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| cypress semiconductor corporation 198 champion court san jose , ca 95134 - 1709 408 - 943 - 2600 document number: 002 - 14910 rev. *e revised july 1, 2016 the following document contains information on cypress products. although the document is marked with the name broadcom , the company that originally developed the specification, cypress will continue to offer these pr oducts to new and existing customers. continuity of specifications there is no change to this document as a result of offering the device as a cypress product. any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. future revisions will occur when appropriate, and changes will be noted in a document history page. continuity of ordering part numbers cypress continues to support existing part numbers. to order these products , please use only the ordering part numbers listed in this document. for more information please visit our website at www .cypress.com or contact your local sales office for additional information about cypress pro ducts and services. our customers cypress is for true innovators C in companies both large and small. our customers are smart, aggressive, out - of - the - box thinkers who design and develop game - changing products that revolutionize their industries or create n ew industries with products and solutions that nobody ever thought of before. about cypress founded in 1982, cypress is the leader in advanced embedded system solutions for the worlds most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. cypresss programmable systems - on - chip, general - purpose microcontrollers, analog ics, wireless and usb - based connectivity solutions and reliable, high - performance memories help engineers design differentiated pro ducts and get them to market first. cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out - of - the - box thinkers to disrupt markets and create new product categories in record tim e. to learn more, go to www.cypress.com .
4319-ds05-r 5300 california avenue ? irvine, ca 92617 ? phone: 949-926-5000 ? fax: 949-926-5203 april 2, 2014 preliminary data sheet bcm4319 single-chip ieee 802.11 ? a/b/g/n mac/baseband/ radio with integrated sdio and usb interfaces figure 1: bcm4319 system block diagram general description general description the broadcom bcm4319 single-chip device provides the highest level of integration for wi-fi enabled sdio and usb-based wireless systems. featuring an ieee 802.11? a/b/g/n mac/baseband/radio with integrated cmos, power amplifiers (pas) and a power management unit (pmu) the bcm4319 provides a compact, ultrasmall form factor solution with few required external components. this enables high- volume costs to be driven down and allows flexibility in the size, form, and function of handheld devices. the bcm4319 supports sdio (4-bit, 1-bit, and serial peripheral interface (spi) modes), generic spi (gspi), usb 2.0 (device), and local bluetooth ? coexistence host interfaces. using advanced design techniques and process technology to deliver the lowest active and idle power, the bcm4319 extends system battery life in mobile systems, while maintaining consistent connectivity and high performance. integrated cmos wlan 2.4 ghz and 5 ghz power amplifiers provide sufficient output power to meet the needs of most wlan devices. an optional external pa and low-noise amplifier (lna) are also supported. in addition, the bcm4319 includes integrated transmit and receive baluns for both the 2.4 ghz and 5 ghz rf paths, further reducing the overall solution cost. to simplify the system power topology and to enable operation directly from the battery of a mobile platform, the bcm4319 includes one switching regulator (buck mode), five linear low dropout (ldo) voltage regulators, and an advanced pmu. a variable input voltage range of 2.7v?5.5v is supported. the integrated buck regulator enables the internal power amplifiers to operate at optimal performance, even at low vbat supply voltages. applications ? usb 2.0 dongles ?printers ? media players ? cellular and mobile phones ? gaming systems ? cameras ? all types of battery powered devices ? integrated designs with bluetooth and gps wl_reg_on sdio uart reference frequency wlan host i/f tcxo 5 g h z w l a n t x 5 g h z w l a n r x 2.4 ghz wlan tx 2 . 4 g h z w l a n r x bcm4319 switch cbf vddio vbat usb switch broadcom ? , the pulse logo, connecting everything ? , and the connecting everything logo are among the trademarks of broadcom corporation and/or its affiliates in the united states, certain other countries and/or the eu. any other trademarks or trade names mentioned are the property of their respective owners. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. broadcom provides this data sheet ?as-is,? without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non- infringement. broadcom corporation 5300 california avenue irvine, ca 92617 ? 2014 by broadcom corporation all rights reserved printed in the u.s.a. features ieee 802.11x key features ? dual band 2.4 ghz and 5 ghz 802.11 a/b/g/n. ? single stream 802.11n support for both 20 mhz and 40 mhz channels provides phy layer rates up to mcs7 (150 mbps) for typical upper layer throughput in excess of 70 mbps. ? integrated cmos power amplifiers deliver greater than 20 dbm of linear output power ? integrated arm ? cortex-m3 processor and on- chip memory for complete wlan subsystem functionality minimizing the need to wake up the applications processor for standard wlan functions. this allows for further minimization of power consumption, while maintaining the capability to field upgrade with future features. ? provides for the following security features: ? wpa? and wpa2? (personal) support for powerful encryption and authentication ? aes and tkip acceleration hardware for faster data encryption and 802.11i compatibility ? cisco ? compatible extension (ccx, ccx 2.0, ccx 3.0, ccx 4.0) certified ? secureeasysetup? for simple wi-fi ? setup and wpa2/wpa security configuration ? provides ieee 802.11d, e (wmm, qos, wmm-ps), h, i, j (k, r, and w in the future). ? supports ieee 802.15.2 external 3-wire and 4-wire coexistence schemes to support additional co-located wireless technologies such as bluetooth ? gps, wimax or uwb. ? provides an ultra-small form factor solution and ultralow power consumption to support low-cost requirements. ? wi-fi protected setup (wps). ? internal fractional npll allows support for a wide range of reference clock frequencies. ? worldwide regulatory support: global products supported with worldwide homologated design. usb 2.0 key features ? support for high speed 480 mbit/s or full speed 12 mbit/s operation ? endpoint management unit ? usb 2.0 protocol engine ? separate endpoint packet buffers with a 512-byte fifo buffer in each direction ? host-to-device communication for bulk, control, and interrupt transfers sdio key features ? supports standard sdio v2.0 (4-bit and 1-bit), and spi mode ? sdio clock rates up to 50 mhz revision history bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 3 general features ? operation with an input voltage ranging from 2.7v to 5.5v using the internal buck switching regulator ? five linear ldo regulators ?on-chip pmu ? programmable dynamic power management ? uart for system debug ? 8 general purpose i/o (gpio) pins ? 138-ball, wafer-level wlbga package (5.74 mm x 4.53 mm x 0.5 mm, 0.4 mm pitch. dimensions are nominal, see figure 18 on page 61 for maximum dimensions) features revision history bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 4 revision history revision date description 4319-ds05-r 4/2/2014 updated: ? table 32: ?ordering information,? on page 82 4319-ds04-r 12/12/11 updated: ? table 32 on page 88 ? converted to latest format template 4319-ds03-r 11/10/09 updated: ? vbat range, global update from 2.3v?5.5v to 2.7v?5.5v ? ?general description? on page ? figure 1, ?bcm4319 system block diagram,? on page i ? ?mobile phone usage model? on page 2 ? figure 3, ?mobile phone system diagram,? on page 2 ? ?power management? on page 3 ? ?voltage regulators? on page 3 ? ?power supply topology? on page 4 ? figure 4, ?power topology example,? on page 5 ? ?low-power shutdown? on page 6 ? table 1, ?crystal oscillator and external frequency reference specifications,? on page 7 ? ?frequency selection? on page 9 ? ?general-purpose input/output interface? on page 10 ? ?sdio v2.0? on page 13 ? figure 8, ?host interface,? on page 14 ? figure 14, ?wlan mac architecture,? on page 22 ? table 4, ?5.79 mm x 4.58 mm 138-ball wlbga,? on page 29 ? table 6, ?138-ball wlbga sign al descriptions,? on page 34 ? ?strapping options and gpio functions? on page 41 ? table 8, ?strapping options,? on page 42 ? table 9, ?environmental characteristics,? on page 43 ? table 10, ?absolute maximum ratings,? on page 43 ? table 11, ?recommended operating conditions and dc characteristics,? on page 44 ? table 12, ?current consumption,? on page 45 ? cellular blocking (deleted) ? section 11, wlan rf specifications, ?introduction? on page 46 ? table 13, ?2.4 ghz band general rf specifications,? on page 46 ? figure 20, ?rf port location,? on page 46 ? table 14, ?2.4 ghz band receiver rf specifications,? on page 47 ? table 15, ?2.4 ghz band transmitter rf specifications,? on page 49 ? table 16, ?2.4 ghz band local oscillator specifications,? on page 51 ? table 18, ?5 ghz receiver sensitivity,? on page 52 revision history bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 5 ? table 21, ?core buck regulator (cbuck),? on page 54 ? table 22, ?internal paldo,? on page 55 ? table 23, ?2.5v ldo (ldo2p5v),? on page 55 ? table 24, ?cldo,? on page 56 ? table 25, ?lnldo1, lnldo2,? on page 57 ? section 13 ?power-up sequence? on page 58 ? figure 21, ?power-up sequence timing diagram,? on page 58 ? table 27, ?gspi timing,? on page 59 ?table 28, ?sdio bus timing para meters (default mode),? on page 60 ? table 29, ?sdio bus timing parameters (high-speed mode),? on page 61 ? table 32, ?ordering information,? on page 65 ? mac features: ??wse? on page23 ? ?txe? on page 23 ? ?rxe? on page 24 ? ?phy description? on page 25 ? signal descriptions, ?138-ba ll wlbga package? on page 34 ? table 6, ?138-ball wlbga sign al descriptions,? on page 34 4319-ds02-r 7/24/09 updated: ? ?sdio key features? on page ii ? table 1, ?crystal oscillator and external frequency reference specifications,? on page 7 ? table 4, ?138-ball wlbga sign al descriptions,? on page 28 ? table 6, ?strapping options,? on page 36 ? table 8, ?environmental characteristics,? on page 37 ? table 10, ?recommended operating conditions and dc characteristics,? on page 38 ? table 13, ?2.4 ghz band general rf specifications,? on page 42 ? table 15, ?2.4 ghz receiver sensitivity,? on page 44 ? table 16, ?2.4 ghz band transmitter rf specifications,? on page 45 ? ?sdio high speed mode timing? on page 59 ? figure 18, ?138-ball wlbga mechanical information,? on page 62 ? table 32, ?ordering information,? on page 63 revision date description revision history bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 6 4319-ds01-r 2/6/09 updated: ? document type header ? general description on page i ?features on page ii ? figure 2, ?bcm4319 block diagram,? on page 1 ? ?voltage regulators? on page 3 ? figure 4, ?power topology example,? on page 4 ? ?power supply topology? on page 4 ? ?crystal interface and clock generation? on page 6 ? table 1, ?crystal oscillator and external frequency reference specifications,? on page 6 ? figure 5, ?recommended oscillator configuration,? on page 7 ? ?one-time-programmable (otp) memory? on page 9 ? section 4 ?global functions? on page 9 (changed section title, was ?system interfaces?) ? ?usb 2.0 device core? on page 10 ? ?sdio v1.2? on page 11 ? section 5 ?usb 2.0 and sdio interfaces? on page 10 (changed section title; was ?usb 2.0 evice core? ? ?sdio v1.2? on page 11 (moved from section 4 ?global functions? to section 5 ?usb 2.0 and sdio interfaces?) ? section 6 ?802.11 a/b/g/n mac and phy? on page 12 (title modified) ? ?phy features? on page 16 ? ?138-ball wlbga pinout? on page 21 ? table 2, ?5.79 mm x 4.58 mm 138-ball wlbga,? on page 20 ? table 3, ?wlbga signal assignments by pin number and x- and y- coordinates,? on page 21 ? table 4, ?138-ball wlbga sign al descriptions,? on page 25 ? section 10 ?operating conditions? on page 33 (changed section title; was ?dc characteristics?) ? ?environmental ratings? on page 33 (was environmantal conditions; moved from section 16 ?package information? on page 51) ? table 7, ?environmental characteristics,? on page 33 revision date description revision history bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 7 ? table 8, ?absolute maximum ratings,? on page 33 ? table 9, ?recommended operating conditions and dc characteristics,? on page 34 ? table 11, ?blocking signals from embedded cellular transmitter at cellular antenna port,? on page 36 ? ?introduction? on page 36 ? table 13, ?2.4 ghz band receiver rf specifications,? on page 38 ? table 14, ?2.4 ghz receiver sensitivity,? on page 38 ? table 17, ?5 ghz band receiver rf specifications,? on page 40 ? table 21, ?core buck regulator (cbuck),? on page 42 ? table 22, ?internal paldo,? on page 43 ? table 23, ?2.5v ldo (ldo2p5v),? on page 43 ? table 24, ?cldo,? on page 44 ? table 25, ?lnldo1, lnldo2,? on page 45 ? figure 14, ?power-up sequence timing diagram,? on page 46 ? figure 15, ?sdio bus timing (default mode),? on page 47 ? figure 16, ?sdio bus timing (high-speed mode),? on page 49 ? figure 17, ?138-ball wlbga mechanical information,? on page 52 added: ?wlbga package ? ?one-time-programmable (otp) memory? on page 9 ? ?bluetooth coexistence interface? on page 9 ? table 6, ?strapping options and gpio functions,? on page 32 ? ?junction temperature estimation and psijt versus thetajc? on page 51 ? table 18, ?ordering information,? on page 53 deleted: ?fcbga package ? ?lpo clock interface? on page 9 ? table 21, ?paldo with ex ternal pnp,? on page 43 ? table 25, ?bandgap reference block (hvbg),? on page 44 ? table 27, ?ldo bandgap reference (ldobg),? on page 45 4319-ds00-r 05/01/08 initial release revision date description table of contents bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 8 table of contents about this document ............................................................................................................................... .13 purpose and audience ........................................................................................................... ............... 13 acronyms and abbreviations..................................................................................................... ............ 13 document conventions ........................................................................................................... .............. 13 technical support ............................................................................................................................... ....... 13 section 1: overview .......................................................................................................... 14 overview ............................................................................................................................... ....................... 14 mobile phone usage model ....................................................................................................................... 15 section 2: power supplies and management ................................................................. 16 power management ............................................................................................................................... ..... 16 voltage regulators ............................................................................................................................... ...... 16 power supply topology ............................................................................................................................. 17 pmu sequencer ............................................................................................................................... ........... 18 low-power shutdown ............................................................................................................................... .19 section 3: frequency references.................................................................................... 20 crystal interface and clock generation ................................................................................................... 20 crystal oscillator ............................................................................................................................... ......... 21 external frequency reference .................................................................................................................. 22 frequency selection ............................................................................................................................... ... 22 frequency trimming ............................................................................................................................... ... 23 section 4: global functions ............................................................................................. 24 general-purpose input/output interface .................................................................................................. 24 uart interface ............................................................................................................................... ............. 24 one-time-programmable (otp) memory ................................................................................................. 24 bluetooth coexistence interface ............................................................................................................... 25 jtag interface ............................................................................................................................... ............. 25 section 5: usb 2.0 and sdio interfaces.......................................................................... 26 usb 2.0 device core ............................................................................................................................... ... 26 sdio v2.0 ............................................................................................................................... ..................... 27 gspi ............................................................................................................................... ............................... 28 spi protocol ................................................................................................................... ....................... 28 command structure .............................................................................................................. ......... 30 write.......................................................................................................................... ..................... 30 write-read ..................................................................................................................... ................ 30 read........................................................................................................................... .................... 30 status ......................................................................................................................... .................... 31 table of contents bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 9 spi host-device handshake...................................................................................................... ........... 33 boot-up sequence ............................................................................................................... ................. 33 section 6: 802.11 a/b/g/n mac and phy.......................................................................... 35 introduction to the ieee 802.11? standard ............................................................................................ 35 mac features ............................................................................................................................... .............. 35 mac description ................................................................................................................ ................... 36 psm ............................................................................................................................ ................... 37 wse ............................................................................................................................ ................... 37 txe ............................................................................................................................ .................... 37 rxe............................................................................................................................ .................... 38 ifs............................................................................................................................ ...................... 38 tsf ............................................................................................................................ .................... 38 nav............................................................................................................................ .................... 39 mac-phy interface.............................................................................................................. .......... 39 phy features ............................................................................................................................... ............... 39 phy description ................................................................................................................ .................... 39 section 7: wlan 802.11 radio subsystem .................................................................... 42 receiver path ............................................................................................................................... ............... 43 transmitter path ............................................................................................................................... .......... 43 calibration ............................................................................................................................... .................... 43 section 8: pin assignments ............................................................................................. 44 5.79 mm x 4.58 mm 138-ball wlbga package ..................................................................................... 44 section 9: pinout and signal descriptions ..................................................................... 45 signal assignments ............................................................................................................................... .... 45 138-ball wlbga pinout .......................................................................................................... .............. 45 signal descriptions ............................................................................................................................... ..... 49 138-ball wlbga package ......................................................................................................... ........... 49 sdio pin descriptions ............................................................................................................................... 54 strapping options and gpio functions ................................................................................................... 55 section 10: operating conditions.................................................................................... 57 environmental ratings .............................................................................................................................. 5 7 absolute maximum ratings ...................................................................................................................... 57 recommended operating conditions and dc characteristics ............................................................. 58 current consumption ............................................................................................................ ................ 59 section 11: wlan rf specifications .............................................................................. 60 introduction ............................................................................................................................... .................. 60 2.4 ghz band general rf specifications ................................................................................................. 60 table of contents bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 10 2.4 ghz band receiver rf specifications ............................................................................................... 61 2.4 ghz band transmitter rf specifications .......................................................................................... 64 2.4 ghz band local oscillator specifications ......................................................................................... 65 5 ghz band rf receiver specifications .................................................................................................. 66 5 ghz band rf transmitter specifications ............................................................................................. 67 5 ghz band local oscillator frequency generator specifications ....................................................... 67 section 12: internal regulator electrical specifications ............................................... 68 core buck regulator (cbuck) ................................................................................................................... 68 paldo ............................................................................................................................... .......................... 69 2.5v ldo (ldo2p5v) ............................................................................................................................... ... 69 cldo ............................................................................................................................... ............................ 70 lnldo1, lnldo2 ............................................................................................................................... ........ 71 section 13: power-up sequence...................................................................................... 72 sdio host timing requirement ................................................................................................................ 72 reset and regulator control signal sequencing .................................................................................... 72 section 14: interface timing specifications ................................................................... 74 gspi timing ............................................................................................................................... ................. 74 sdio default mode timing ........................................................................................................................ 75 sdio high speed mode timing ................................................................................................................. 76 section 15: usb interface timing specifications........................................................... 78 usb 2.0 electrical and timing parameters .............................................................................................. 78 section 16: package information ..................................................................................... 80 package thermal characteristics ............................................................................................................. 80 junction temperature estimation and psijt versus thetajc....................................................... 80 section 17: mechanical information . ............................................................................... 81 138-ball wlbga package .......................................................................................................................... 81 section 18: ordering information .................................................................................... 82 list of figures bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 11 list of figures figure 1: bcm4319 system block diagram .......................................................................................... ............ 1 figure 2: bcm4319 block diagram ................................................................................................. ................ 14 figure 3: mobile phone system diagram ........................................................................................... ............. 15 figure 4: power topology example................................................................................................ ................. 18 figure 5: recommended oscillator configuration .................................................................................. ......... 22 figure 6: recommended tcxo connection ........................................................................................... ........ 22 figure 7: usb 2.0 device block diagram .......................................................................................... .............. 26 figure 8: host interface ........................................................................................................ ........................... 28 figure 9: spi write protocol .................................................................................................... ........................ 29 figure 10: spi read protocol .................................................................................................... ...................... 29 figure 11: spi command structure................................................................................................ ................. 30 figure 12: spi signal timing without status..................................................................................... .............. 31 figure 13: spi signal timing with status (response delay = 0)................................................................... .. 32 figure 14: wlan mac architecture ................................................................................................ ................ 36 figure 15: wlan phy block diagram............................................................................................... .............. 40 figure 16: stbc receive block diagram........................................................................................... ............. 41 figure 17: radio functional block diagram ....................................................................................... ............. 42 figure 18: signal connections to sdio card (sd 4-bit mode) ...................................................................... .55 figure 19: signal connections to sdio card (gspi mode) .......................................................................... ... 55 figure 20: rf port location..................................................................................................... ........................ 60 figure 21: power-up sequence timing diagram ..................................................................................... ....... 73 figure 22: gspi timing .......................................................................................................... .......................... 74 figure 23: sdio bus timing (default mode) ....................................................................................... ............ 75 figure 24: sdio bus timing (high-speed mode).................................................................................... ........ 76 figure 25: 138-ball wlbga mechanical information ................................................................................ ...... 81 list of tables bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 12 list of tables table 1: crystal oscillator and external frequency reference specifications ................................................ 20 table 2: spi status field details ............................................................................................... ...................... 32 table 3: spi registers .......................................................................................................... ........................... 33 table 4: 5.79 mm x 4.58 mm 138-ball wlbga ....................................................................................... ........ 44 table 5: wlbga signal assignments by pin number and x- and y-coordinates .......................................... 45 table 6: 138-ball wlbga signal descriptions ..................................................................................... ........... 49 table 7: sdio pin descriptions .................................................................................................. ..................... 54 table 8: strapping options ...................................................................................................... ........................ 56 table 9: environmental characteristics .......................................................................................... ................. 57 table 10: absolute maximum ratings .............................................................................................. ............... 57 table 11: recommended operating conditions and dc characteristics ........................................................ 58 table 12: current consumption................................................................................................... .................... 59 table 13: 2.4 ghz band general rf specifications................................................................................ ........ 60 table 14: 2.4 ghz band receiver rf specifications ............................................................................... ....... 61 table 15: 2.4 ghz band transmitter rf specifications ............................................................................ ...... 64 table 16: 2.4 ghz band local oscillator specifications.......................................................................... ........ 65 table 17: 5 ghz band receiver rf specifications ................................................................................. ........ 66 table 18: 5 ghz receiver sensitivity ............................................................................................ .................. 66 table 19: 5 ghz band transmitter rf specifications .............................................................................. ....... 67 table 20: 5 ghz band local oscillator frequency generator specifications ................................................. 67 table 21: core buck regulator (cbuck)........................................................................................... ............. 68 table 22: internal paldo ........................................................................................................ ........................ 69 table 23: 2.5v ldo (ldo2p5v) .................................................................................................... .................. 69 table 24: cldo .................................................................................................................. ............................. 70 table 25: lnldo1, lnldo2 ........................................................................................................ ................... 71 table 26: power management unit ................................................................................................. ................ 71 table 27: gspi timing ........................................................................................................... .......................... 74 table 28: sdio bus timing parameters (default mode) ............................................................................ .... 75 table 29: sdio bus timing parameters (high-speed mode) ........................................................................ 7 7 table 30: usb 2.0 electrical and timing parameters............................................................................... ....... 78 table 31: 138-ball wlbga package thermal characteristics ........................................................................................... 80 table 32: ordering information .................................................................................................. ...................... 82 broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 13 bcm4319 preliminary data sheet about this document purpose and audience this data sheet provides details about the functional, operational, and electrical characteristics of the broadcom bcm4319. it is intended for hardware design, application, and oem engineers. acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. for a comprehensive list of acronyms and other terms used in broadcom documents, go to: http://www.broadcom.com/press/glossary.php . document conventions the following conventions may be used in this document: technical support broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, pcb layout information, and software updates through its customer support portal ( https://support.broadcom.com ). for a csp account, contact your sales or engineering support representative. in addition, broadcom provides other product support through its downloads & support site ( http://www.broadcom.com/support/ ). convention description bold user input and actions: for example, type exit , click ok, press alt+c monospace code: #include command line commands and parameters: wl [-l] |
overview bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 14 section 1: overview overview the broadcom bcm4319 family of single-chip devices provides the highest level of integration for a mobile or handheld wireless system, with integrated ieee 802.11? a/b/g/n (mac/baseband/radio), power amplifiers (pas), and power management unit (pmu). it provides a compact, small form factor solution with minimal external components to drive down the costs for mass volumes while enabling handheld device flexibility in size, form, and function. the bcm4319 is designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation. figure 2 shows the major blocks and external interfaces of the bcm4319. figure 2: bcm4319 block diagram bcm4319 usb2.0/1.1 device por xtal power supply power supply lpo switching regulator ldo xtal oscillator por ram (288 kb) rom (128 kb) axi backplane arm ? cm3 jtag 2 kb otp uart jtag wdog timer gpio gpio uart jtag 802.11 a/b/g/n mac sslpnphy 5 ghz 2.4 ghz radio pa (int) pa (int) u s b sdio/spi sdiod spi pmu ctrl mobile phone usage model bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 15 mobile phone usage model the bcm4319 has a flexible universal serial bus (usb) and a secure digital input/output (sdio) interface for cellular phone applications, enabling it to transparently connect to existing circuits. in addition, the temperature- compensated crystal oscillator (tcxo) input allows the use of existing clock sources within the system to further minimize the size, power, and cost of the complete system. the bcm4319 incorporates the following unique features for easy integration into mobile phone platforms: ? the tcxo interface accommodates typical cell phone reference frequencies. ? the transceiver?s highly linear design ensures the lowest spurious output regardless of operating state. it has been fully characterized in all global cellular bands. ? the transceiver design, with minimal required external filtering, has excellent blocking and intermodulation performance in the presence of the following cellular transmissions: ? global standard for mobile communications (gsm) ? general packet radio service (gprs) ? code division multiple access (cdma) ? wideband cdma (wcdma) ? integrated digital enhanced network (iden). ? minimal external components are required for integration; compact packaging is available. the bcm4319 is designed to interface directly with new and existing handset designs as shown in figure 3 . figure 3: mobile phone system diagram wl_reg_on sdio uart reference frequency wlan host i/f tcxo 5 g h z w l a n t x 5 g h z w l a n r x 2.4 ghz wlan tx 2 . 4 g h z w l a n r x bcm4319 switch cbf vddio vbat usb switch power supplies and management bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 16 section 2: power supplies and management power management the bcm4319 has been designed with the stringent power consumption requirements of mobile devices in mind. all areas of the chip design are optimized to minimize power consumption. silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. additionally, the bcm4319 integrated ram is a high vt memory with dynamic clock control. leakage current is the dominant supply current consumed by the ram. the bcm4319 includes an advanced wireless local area network (wlan) pmu. the pmu provides significant power savings by putting the bcm4319 into various power management states appropriate to the current environment and activities that are being performed. the power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and the relationship between resources and the time needed to enable and disable them. power-up sequences are fully programmable. configurable, free-running counters (running on an internal lpo clock) in the pmu are used to turn individual regulators and power switches on and off. clock speeds are dynamically changed or gated for the current mode. slower clock speeds are used wherever possible. the bcm4319 power states are described as follows: ? active mode?all bcm4319 cores are powered up and fully functional with active carrier sensing, frame transmission, and frame reception. all required regulators are enabled and put in the most efficient mode, either pulse width modulation (pwm) or burst, based on the load current. clock speeds are dynamically adjusted by the pmu. ? sleep mode?the radio, analog front end (afe), phase-locked loops (plls), and read-only memories (roms) are powered down. the rest of the bcm4319 remains powered up in an idle state. all main clocks are shut down. the internal 32 khz clock is used by the pmu to wake the chip and transition to active mode. in sleep mode, the primary power consumed is due to leakage current. the internal baseband switcher is put into burst mode for better efficiency at low load currents. ? power-down mode?the bcm4319 is effectively powered off by shutting down all internal regulators. the chip is brought out of this mode by external logic re-enabling the internal regulators. voltage regulators one buck regulator, five ldo regulators, and a pmu are integrated into the bcm4319. all regulators are programmable via the pmu. ? core buck: 2.7?5.5v in; 1.4v, 300 ma out ? low-noise lnldo1: 1.4v in; 1.2v, 150 ma out ? low-noise lnldo2 (optional): 1.4v or 3.3v in; 1.2v or 2.5v, 50 ma out ? low-noise cldo: 1.4v in; 1.2v, 200 ma out power supply topology bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 17 ? paldo: 2.7?5.5v in; 2.7?4.0v, 400 ma out ? ldo2p5v: 2.7 ? 5.5v in; 2.5v, 50 ma out for usb2.0 phy power supply topology the bcm4319 contains power supply building blocks, including a switching regulator, four ldos, and a power amplifier ldo (see figure 4 on page 18 ). these blocks simplify power supply design for wlan in embedded designs. all regulator inputs and outputs are brought out to pins on the bcm4319, thereby enabling maximum system design flexibility in choosing which of the integrated regulators to use. a single host power supply, ranging from 2.7v to 5.5v, can be used with all additional voltages being provided by bcm4319 regulators. for additional information see section 12: ?internal regulator electrical specifications,? on page 68 . alternately, if specific rails such as 3.3v, 2.5v, and 1.2v already exist in the system, appropriate regulators in the bcm4319 can be disabled, thereby reducing the cost and board space associated with external regulator components such as inductors and large capacitors. when wl_reg_on is low (< 1.2 ? 20% = 0.96v) or the voltage at vddio is less than 0.96v, all six regulators are powered down. when wl_reg_on is high (> 1.6v) and the voltage at vddio is greater than 1.6v, the cbuck, ldo2p5v, cldo, and lnldo1 regulators are powered on by default. the digital logic remains in the reset state while ext_por_l is low or while the internal por is asserted. the internal por circuit generates a reset within 110 ms after vddc and vddio stabilize. after the resets are deasserted, the bcm4319 powers up the paldo, otp, and clock circuitry. after the digital logic is active and the software is running, the state of all the regulators is controlled dynamically. to keep the digital logic powered up, cbuck and cldo cannot be powered down. they can, however, be put into low-power modes. the paldo can be powered on or off under software control to reduce power consumption, for example during sleep mode. there is a 200 k (20%) internal pull-down on wl_reg_on, which can be disabled after the digital logic is active. ? the voltage at wl_reg_on should not exceed 3.6v. ? the io supply for the ext_por_l pin is vddio. ? vbat and vddio should be supplied externally: vddio cannot be supplied by the output of any of the six regulators. ? the por delays are different for the three io supplies: ? vddio = 110 ms ? vddio_sd = 8 us ? vddio_rf = 3.4 ms the trip point of the internal por circuit is vddc ~ 0.8v or vddio/vddio_sd/vddio_rf ~ 0.9v and the ios remain in tristate during the respective por. pmu sequencer bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 18 figure 4: power topology example pmu sequencer the pmu sequencer is responsible for minimizing system power consumption. it enables and disables various system resources based on a computation of the required resources and the relationship between resources and their enable and disable times. in each device state, a minimum set of resources is always available, as defined in the pmu control registers. additional resources can be enabled on request from various sources, including clock requests from cores and timers in any of the active resources. the pmu sequencer maps clock requests into a set of resources required to produce the requested clocks. bcm4319 bcm4319 bcm4319 wl radio rf pll wl afe xtal core logic blocks wl radio (noise insensitive) wl digital wl otp (optional) ln ld02 input: 1.4 or 3.3v output: 1.2 or 2.5-3.1v, 50 ma internal wlan power amplifier 1 . 4 v 1.2v ln ld01 input: 1.4v output:1.2v 150 ma cldo input: 1.4v output:1.2v 200 ma vddio 1.8 to 3.3v core buck regulator (300 ma) paldo (3.3v, 400 ma) vddio_rf vbat 2.7v - 5.5v note : shaded areas are internal to the bcm4319. 1 . 2 v afe: analog front end otp: one-time programmable memory pll: phase-locked loop wl: wireless lan usb 2.0 phy, other internal blocks ldo2p5 2.5v 50 ma vddio and vddio_sd usbphy 3.3v usb low-power shutdown bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 19 each resource is in one of four states: enabled, disabled, transition_on, and transition_off. each resource has a timer that contains 0 when the resource is enabled or disabled and a nonzero value in the transition states. the timer is loaded with the resource's time_on or time_off value when the pmu determines that the resource must be enabled or disabled, and it decrements on each 32.768 khz pmu clock. when it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. if the time_on value is 0, the resource can go immediately from disabled to enabled. similarly, a time_off value of 0 indicates that the resource can go immediately from enabled to disabled. the terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. during each clock cycle, the pmu sequencer performs the following: 1. computes the required resource set based on requests and the resource dependency table. 2. decrements all timers whose values are nonzero. if a timer reaches 0, the pmu clears the resourcepending bit for the resource and inverts the resourcestate bit. 3. compares the request with the current resource status and determines which resources must be enabled or disabled. 4. initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents. 5. initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. low-power shutdown the bcm4319 provides a low-power shutdown feature that allows the device to be turned off while the host and other system devices remain operational. when the bcm4319 is not needed in the system, wl_reg_on should be driven low while vddio remains powered. this allows the bcm4319 to be effectively off while keeping the i/o pins powered, so that they do not draw extra current from any other devices connected to the i/ o. during a low-power shutdown state, provided vddio remains applied to the bcm4319, all outputs are tristated, and most inputs signals are disabled. input voltages must remain within the limits defined for normal operation. this is done to prevent current paths or to create loading on any digital signals in the system, and it enables the bcm4319 to be fully integrated in an embedded device and to take full advantage of the lowest power saving modes. the frequency reference input (xtalin) is designed to be a high-impedance input that does not load down the driving signal, even if the chip does not have vddio power applied to it. when the bcm4319 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about its state from before it was powered down. frequency references bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 20 section 3: frequency references the bcm4319 uses the following frequency references for normal and low-power operational modes: ? an external crystal or external frequency reference driven by a tcxo signal is used for generating all radio frequencies and normal operation clocking. ? an internal 32.768 khz sleep clock is provided for use by the pmu during low power states. crystal interface and clock generation the bcm4319 uses a fractional-n synthesizer to generate the radio frequencies, clocks, and data/packet timing. this enables it to operate using numerous frequency references derived from an external source such as a tcxo or a crystal connected directly to the bcm4319. the default frequency reference is a 30 mhz, 10 ppm crystal or tcxo. the requirements and characteristics for the crystal circuit and external frequency reference are listed in ta b l e 1 . table 1: crystal oscillator and external frequency reference specifications parameter condition a crystal external frequency reference unit min typ max min typ max frequency ? ? 30 ? 12 30 52 mhz b esr ? ??60?n/a? input impedance resistive ? n/a 1m ? ? capacitive ? n/a ? 4.7 pf power dissipation programmable depends on external reference input amplitude 0.2?10.2?1mw input voltage ac-coupled analog signal ? n/a 400 c ? 1200 mv p-p output low level dc-coupled digital signal ? n/a 0 ? v output high level dc-coupled digital signal ? n/a 1.0 ? 1.36 v frequency tolerance d without trimming ?20 + 10 20 ?20 + 10 20 ppm initial frequency tolerance trimming range ? ?50?50?50?50ppm duty cycle for 30 mhz clock ? n/a ? 40 50 60 % crystal oscillator bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 21 crystal oscillator the bcm4319 can use an external crystal to provide a frequency reference. the recommended configuration for the crystal oscillator including all external components is shown in table 5 on page 22 . refer to the reference board schematics for exact details. phase noise requirements e f for 30 mhz clock ? n/a ? ? ?130 g ?dbc/hz for 30 mhz clock ? n/a ? ? ?140 f ?dbc/hz for 30 mhz clock ? n/a ? ? ?145 f ?dbc/hz for 30 mhz clock ? n/a ? ? ?150 f ?dbc/hz jitter from1 khz to 1 mhz ?n/a???< 0.33 ps a. the supported crystal/external reference frequencies for sdio mode are 12 mhz to 52 mhz (26 or 30 mhz is recommended). for usb mode, only 30 mhz is supported. b. frequency programmable between 12 mhz and 52 mhz, in 2 ppm steps. the step size (resolution) is approximately 80 hz. c. exact value of load capacitance to center the frequency tolerance depends on board layout; see broadcom reference schematics. d. initial + over temperature + aging. e. if the input signal amplitude is below 800 mv p-p, contact your broadcom representative for applications assistance. f. for a clock reference other than 30 mhz, these limits must be scaled by 20*log10( f / 30 ) db, where f = the reference clock frequency in mhz. g. for 5 ghz, 11n (both the 20 and 40 mhz channels): covers all other modes of operation. table 1: crystal oscillator and external frequency reference specifications (cont.) parameter condition a crystal external frequency reference unit min typ max min typ max external frequency reference bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 22 figure 5: recommended oscillator configuration external frequency reference an external frequency reference generated by a tcxo may be directly connected to the xtalin pin on the bcm4319 as shown in figure 6 . the external frequency reference input is designed to not change the loading on the tcxo when the bcm4319 is powered up or powered down. figure 6: recommended tcxo connection frequency selection for sdio mode, any frequency within the ranges specified for the crystal and tcxo reference may be used. these include the standard handset reference frequencies of 12, 13, 14.4, 16.2, 16.8, 18, 19.2, 19.44, 19.68, 19.8, 20, 24, 26, 30, 38.4, and 52 mhz, plus any other frequency in this range. the bcm4319 must have the reference frequency set correctly in order for any of the uart interfaces to function properly, since all bit timing is derived from the reference frequency. a. the precise value of load capacitance to center the frequency tolerance is dependent on board layout; see broadcom reference schematics for exact values. xtalin xtalout 30 mhz 10 ppm c c 10 ? 33 pf a 10 ? 33 pf a tcxo no connection * recommended value is 100 pf. higher values produce a longer start-up time. 33 pf-1000 pf * xtalin xtalout frequency trimming bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 23 the bcm4319 is set at the factory to a default frequency of 30 mhz. for a typical design using a crystal, it is recommended that the default frequency be used: for usb mode, 30 mhz is required . frequency trimming the bcm4319 uses a fractional-n synthesizer to digitally fine tune the frequency reference input to within 2 ppm tuning accuracy. this trimming function can be applied to the crystal or an external frequency source such as a tcxo. unlike typical crystal trimming methods, the bcm4319 uses a fully digital implementation to change the frequency, which is much more stable and tolerant of the crystal characteristics and temperature. the input impedance and loading characteristics remain unchanged on either the tcxo or the crystal during the trimming process and are unaffected by process and temperature variations. global functions bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 24 section 4: global functions general-purpose input/output interface there are eight general-purpose i/o (gpio) pins on the bcm4319, which can be used to control various external devices. upon power-up and reset, these pins become tri-stated. subsequently, they can be programmed to be either input or output pins via the gpio control register. if a gpio output enable is not asserted and the corresponding gpio signal is not being driven externally, then the gpio is read as high. each gpio has a programmable option to enable/disable internal pull-up or pull-down (60 k ) resistors. the default setting depends on the strapping options: if a strapping option is assigned to a gpio pin then the default pull is according to the default strapping value. otherwise, there is no default pull on the gpio. gpios that do not have interfering strapping options can be safely used as input pins. all gpios can be safely used in output mode. internal pull-up and pull-down resistors are active only when vddc and vddio are present. after the driver is loaded, the software disables the pull to reduce leakage. uart interface one uart interface is provided, which enables the bcm4319 to operate as rs-232 data termination equipment (dte) for exchanging and managing data with other serial devices. the uart interface is primarily used for debugging during development. it is compatible with the industry standard 16550 uart, and it provides a fifo size of 64 8 in each direction. one-time-programmable (otp) memory various hardware configuration parameters may be stored in an internal 2k-bit otp memory, which is read by system software after device reset. in addition, customer-specific parameters, including the system vendor id and the mac address, can be stored, depending on the specific board design. a programming utility is provided with the broadcom manufacturing test tools. as an alternative to using the internal otp, an external 4-wire sprom interface can be enabled. bluetooth coexistence interface bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 25 bluetooth coexistence interface a 4-wire handshake interface is provided to enable signaling between the device and an external colocated wireless device, such as bluetooth gps, wimax or uwb, to manage wireless medium sharing for optimum performance. the ieee 802.15.2 coexistence schemes can be supported. the following signals are provided: ? btcx_status ? btcx_rf_active ? btcx_freq ? btcx_txconf jtag interface the bcm4319 supports the ieee 1149.1 jtag boundary scan standard for testing the device packaging and pcb during manufacturing. it is also an essential interface for broadcom to run characterization tests and it is highly recommended to provide access to these pins on all pcb designs. usb 2.0 and sdio interfaces bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 26 section 5: usb 2.0 and sdio interfaces usb 2.0 device core the usb 2.0 device core is enabled by a strapping option, see table 8 on page 56 for details. it includes the following features: includes the following features: ? support for high speed at 480 mbit/s or full speed at 12 mbit/s operation ? usb 2.0 transceiver interface ? data and clock recovery circuit ? bit stuffing and unstuffing; bit stuff error detection ? sync/eop generation and checking ? error detection and handling ? wake up, resume, and suspend detection ? endpoint management unit?manages usb traffic and dma engine ? usb 2.0 protocol engine ? parallel interface engine (pie) between packet buffers and usb transceiver ? supports up to nine endpoints, including configurable control endpoint 0 ? separate endpoint packet buffers, each with a 512-byte first-in first-out (fifo) buffer ? host-to-device communication for bulk, control, and interrupt transfers ? configuration/status registers the blocks in the usb 2.0 device core are shown in figure 7 . figure 7: usb 2.0 device block diagram usb 2.0 device 32-bit on-chip communication system dma engines rx fifo tx fifos tx fifos tx fifos tx fifos tx fifos tx fifos endpoint management unit usb 2.0 protocol engine usb 2.0 phy d + d - sdio v2.0 bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 27 the usb 2.0 phy handles the usb protocol and the serial signaling interface between the host and the device. it is primarily responsible for data transmission and recovery. on the transmit side, data and a clock are encoded using the nrzi scheme with bit stuffing to ensure that the receiver detects a transition in the data stream. a sync field that precedes each packet enables the receiver to synchronize the data and clock recovery circuits. on the receive side, the serial data is deserialized, unstuffed, and checked for errors. the recovered data and clock are then shifted to the clock domain that is compatible with the internal bus logic. the endpoint management unit contains the pie control logic and the endpoint logic. the pie interfaces the packet buffers to the usb transceiver. it handles packet identification (pid), usb packets, and transactions. the endpoint logic contains nine uniquely addressable endpoints. these endpoints are the source or sink of communication flow between the host and the device. endpoint zero is used as a default control port for both the input and output directions. the usb system software uses this default control method to initialize and configure the device information and allows usb status and control access. endpoint zero is always accessible after a device is attached, powered, and reset. endpoints are supported by 512-byte fifo buffers, one for each in endpoint and one shared by all out endpoints. both tx and rx data transfers support a dma burst of 4, which guarantees low latency and maximum throughput performance. the rx fifo can never overflow by design. the maximum usb packet size cannot be more than 512 bytes. sdio v2.0 the sdio interface is enabled by a strapping option, see table 8 on page 56 for details. the bcm4319 supports all of the sdio version 2.0 modes: ? 1-bit sdio-spi mode (25 mbps) ? 1-bit sdio-sd mode (25 mbps) ? 4-bit sdio-sd default speed mode (100 mbps) ? 4-bit sdio-sd high speed mode (200 mbps) the sdio interface supports the full clock range, from 0 to 50 mhz. the chip has the ability to stop the sdio clock between transactions to reduce power consumption. as an option, gpio_0 pin may be mapped to provide an sdio interrupt signal. this out-of-band interrupt is hardware generated and is always valid (unlike the sdio in-band interrupt, which is signalled only when data is not driven on sdio lines).the ability to force control of the gated clocks from within the wlan chip is also provided. three functions are supported: ? function 0 standard sdio function. maximum blocksize/bytecount = 32 bytes. ? function 1 backplane function to access the internal system-on-a-chip (soc) address space. maximum blocksize/bytecount = 64 bytes. ? function 2 wlan function for efficient wlan packet transfer through direct memory access (dma). maximum blocksize/bytecount = 512 bytes. detailed sdio pin description and signal connection block diagrams are shown in section 9: ?pinout and signal descriptions,? on page 45 . in addition, the generic spi (gspi) mode, with clock ranges from 0 to 48 mhz, is supported. gspi bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 28 gspi the bcm4319 also includes the generic spi (gspi) interface/protocol functionality. characteristics of the bcm4319 interface includes support for: ? up to 48 mhz operation ? fixed delays for responses and data from device ? alignment to host spi frames (16- or 32-bits) ? up to 2 kb frame size per transfer ? little endian and big endian configurations ? configurable active edge for shifting ? packet transfer through dma for wlan figure 8: host interface spi protocol the spi protocol supports both 16-bit and 32-bit word operation. byte endianess is supported in both modes. figure 9 and figure 10 show the basic write and write-read commands. host wlan spi_clk/sdio_clk spi_din/sdio_cmd spi_dout/sdio_data_0 spi_csx/sdio_data_3 wlan_irq (sdio_data_1 or gpio_0) clk_req/xtal_pu ref_clk/xtalin wlan_enable/wl_reg_on gspi bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 29 figure 9: spi write protocol figure 10: spi read protocol gspi bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 30 command structure the spi command structure is 32 bits. the bit positions and definitions are as shown in figure 11 . figure 11: spi command structure write the host puts the first bit of the data onto the bus one-half clock-cycle before the first active edge following the cs going low. the following bits are clocked out on the falling edge of the spi clock. the device samples the data on the active edge. write-read the host reads on the rising edge of the clock requiring data from the device to be made available before the first rising clock edge of the clock burst for the data. the last clock edge of the fixed delay word can be used to represent the first bit of the following data word. this allows data to be ready for the first clock edge without relying on asynchronous delays. read the read command always follows a separate write to set up the wlan device for a read. this command differs from the write-read command in the following respects: a) chip selects go high between the command/address and the data and b) the time interval between the command/address is not fixed. 0 10 27 11 packet length - 11bits * address C 17 bits f1 f0 c a function no: 00 C func 0 01 C func 1 10 C func 2 11 C func 3 command : 0 C read 1 C write bcm_spid command structure 28 29 30 31 access : 0 C fixed address 1 C incremental address * 11h0 = 2048 bytes 0 10 27 11 packet length - 11bits * address C 17 bits f1 f0 c a function no: 00 C func 0: all spi specific registers 01 C func 1: registers and meories belonging to other blocks in the chip (64 bytes max) 10 C func 2: dma channel 1. wlan packets up to 2048 bytes. 11 C func 3: dma channel 2 (optional). packets up to 2048 bytes. command : 0 C read 1 C write bcm_spid command structure 28 29 30 31 access : 0 C fixed address 1 C incremental address * 11h0 = 2048 bytes gspi bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 31 status the spi interface supports status notification to the host after a read/write transaction. this status notification provides information about any packet errors, protocol errors, information about available packet in the rx queue, etc. the status information helps in reducing the number of interrupts to the host. the status-reporting feature can be switched off using a register bit, without any timing overhead. the spi bus timing for read/write transactions with and without status notification are as shown in figure 12 and figure 13 on page 32 . see table 2 on page 32 for information on status field details. figure 12: spi signal timing without status c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits cs sclk mosi c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay d1 c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits cs sclk mosi c31 c30 c1 c0 d31 d30 d1 d0 c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits cs sclk mosi c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay d1 c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso cs sclk mosi response delay d1 write write-read read gspi bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 32 figure 13: spi signal timing with status (response delay = 0) table 2: spi status field details bit name description 0 data not available the requested read data is not available 1 underflow fifo underflow occurred due to current (f2, f3) read command 2 overflow fifo overflow occurred due to current (f1, f2, f3) write command 3 f2 interrupt f2 channel interrupt 4 f3 interrupt f3 channel interrupt 5 f2 rx ready f2 fifo is ready to receive data (fifo empty) 6 f3 rx ready f3 fifo is ready to receive data (fifo empty) 7 reserved ? 8 f2 packet available packet is available/ready in f2 tx fifo 9:19 f2 packet length length of packet available in f2 fifo 20 f3 packet available packet is available/ready in f3 tx fifo 21:31 f3 packet length length of packet available in f3 fifo c31 c0 d31 d1 d0 read data 16*n bits miso cs sclk mosi s0 s31 status 32 bits c31 c0 d31 d1 d0 command 32 bits read data 16*n bits miso cs sclk mosi s0 s31 status 32 bits c31 s0 c1 c0 d31 s31 d1 d0 command 32 bits write data 16*n bits cs sclk mosi s1 status 32 bits miso c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 s0 c1 c0 d31 s31 d1 d0 s1 c31 s0 c1 c0 d31 s31 d1 d0 s1 command 32 bits write write-read read gspi bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 33 spi host-device handshake to initiate communication through the spi after power-up, the host needs to bring up the wlan/chip by writing to the wake-up wlan register bit. writing a 1 to this bit will start up the necessary crystals and plls so that the bcm4319 is ready for data transfer. the device can signal an interrupt to the host indicating that the device is awake and ready. this procedure also needs to be followed for waking up the device in sleep mode. the device can interrupt the host using the wlan irq line whenever it has any information to pass to the host. on getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of interrupt and then take necessary actions. boot-up sequence after power-up, the spi host needs to wait for the device to be out of reset. for this, the host needs to poll with a read command to f0 addr 0x14. address 0x14 contains a predefined bit pattern. as soon as the host gets a response back with the correct register content, it implies that the device has powered up and is out of reset. after that, the host needs to set wakeup-wlan bit (f0 reg 0x00 bit 7). wakeup-wlan issues a clock request to the pmu. for the first time after power-up, the host needs to wait for the availability of low power clock inside the device. once that is available, the host needs to write to a pmu register to set the crystal frequency. this will turn on the pll. after the pll is locked, chipactive interrupt is issued to the host. this indicates device awake/ready status. see ta b le 3 for information on spi registers. in ta b le 3 , the following notation is used for register access: ? r: readable from host and cpu ? w: writable from host ? u: writable from cpu table 3: spi registers address register bit access default description x0000 word length 0 r/w/u 0 0 ? 16 bit word length 1 ? 32 bit word length endianess 1 r/w/u 0 0 ? little endian 1 ? big endian high speed mode 4 r/w/u 1 0 ? normal mode. rx and tx at different edges. 1 ? high speed mode. rx and tx on same edge (default). interrupt polarity 5 r/w/u 1 0 ? interrupt active polarity is low 1 ? interrupt active polarity is high (default) wake-up 7 r/w 0 a write of 1 will denote wake-up command from host to device. this will be followed by a f2 interrupt from spi device to host, indicating device awake status. x0001 response delay 7:0 r/w/u 8?h04 configurable read response delay in multiples of 8 bits gspi bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 34 x0002 status enable 0 r/w 1 0 ? no status sent to host after read/write 1 ? status sent to host after read/write interrupt with status 1 r/w 0 0 ? do not interrupt if status is sent 1 ? interrupt host even if status is sent response delay for all 2 r/w 0 0 ? response delay applicable to f1 read only 1 ? response delay applicable to all function read x0003 reserved x0004 interrupt register 0 r/w 0 requested data not available; cleared by writing a 1 to this location 1 r 0 f2/f3 fifo underflow due to last read 2 r 0 f2/f3 fifo overflow due to last write 5 r 0 f2 packet available 6 r 0 f3 packet available 7 r 0 f1 overflow due to last write x0005 interrupt register 5 r 0 f1 interrupt 6 r 0 f2 interrupt 7 r 0 f3 interrupt x0006 - x0007 interrupt enable register 15:0 r/w/u 16'he0e7 particular interrupt is enabled if a corresponding bit is set x0008 - x000b status register 31:0 r 32'h0000 same as status bit definitions x000c - x000d f1 info register 0 r 1 f1 enabled 1 r 0 f1 ready for data transfer 13:2 r/u 12'h40 f1 max packet size x000e - x000f f2 info register 0 r/u 1 f2 enabled 1 r 0 f2 ready for data transfer 15:2 r/u 14'h800 f2 max packet size x0010 - x0011 f3 info register 0 r/u 1 f3 enabled 1 r 0 f3 ready for data transfer 15:2 r/u 14'h800 f3 max packet size x0014 - x0017 test?read only register 31:0 r 32'hfee dbead this register contains a predefined pattern, which the host can read and determine if the spi interface is working properly. x0018 - x001b test?r/w register 31:0 r/w/u 32'h0000 0000 this is a dummy register where the host can write some pattern and read it back to determine if the spi interface is working properly. table 3: spi registers (cont.) address register bit access default description 802.11 a/b/g/n mac and phy bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 35 section 6: 802.11 a/b/g/n mac and phy introduction to the ieee 802.11? standard the ieee 802.11? standard defines two different ways to configure a wireless network: ad hoc mode and infrastructure mode. in ad hoc mode, nodes are brought together to form a network on the fly, whereas infrastructure mode uses fixed access points through which mobile nodes can communicate. these network access points are sometimes connected to wired networks through bridging or routing functions. the medium access control (mac) layer is a contention resolution protocol that is responsible for maintaining order in the use of a shared wireless medium. ieee 802.11 specifies both contention-based and contention-free channel access mechanisms. the contention-based scheme is also called the distributed coordination function (dcf) and the contention-free scheme is also called the point coordination function (pcf). the dcf employs a carrier sense multiple access with collision avoidance (csma/ca) protocol. in this protocol, when the mac receives a packet to be transmitted from its higher layer, the mac first listens to ensure that no other node is transmitting. if the channel is clear, it then transmits the packet. otherwise, it chooses a random backoff factor that determines the amount of time the node must wait until it is allowed to transmit its packet. during periods in which the channel is clear, the mac waiting to transmit decrements its backoff counter, and when the channel is busy, it does not decrement its backoff counter. when the backoff counter reaches zero, the mac transmits the packet. because the probability that two nodes will choose the same backoff factor is low, collisions between packets are minimized. collision detection, as employed in ethernet, cannot be used for the radio frequency transmissions of devices following ieee 802.11. the ieee 802.11 nodes are half-duplex? when a node is transmitting, it cannot hear any other node in the system that is transmitting because its own signal drowns out any others arriving at the node. optionally, when a packet is to be transmitted, the transmitting node can first send out a short request to send (rts) packet containing information on the length of the packet. if the receiving node hears the rts, it responds with a short clear to send (cts) packet. after this exchange, the transmitting node sends its packet. when the packet is received successfully, as determined by a cyclic redundancy check (crc), the receiving node transmits an acknowledgment (ack) packet. this back and forth exchange is necessary to avoid the hidden node problem. hidden node is a situation where node a can communicate with node b, node b can communicate with node c, but node a cannot communicate with node c. for instance, although node a can sense that the channel is clear, node c can be transmitting to node b. this protocol alerts node a that node b is busy, and that it must wait before transmitting its packet. mac features the bcm4319 wlan mac supports features specified in the 802.11 base standard plus those amended by 802.11n. the salient features are listed below: ? transmission and reception of aggregated mac protocol data units (a-mpdus) ? support for power management schemes, including wi-fi multimedia? (wmm ? ) power save, power save multipoll (psmp) and multiphase psmp operation ? support for immediate ack and block-ack policies mac features bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 36 ? interframe space timing support, including reduced interframe spacing (rifs) ? support for rts/cts and cts-to-self frame sequences for protecting frame exchanges ? back-off counters in hardware for supporting multiple priorities as specified in the wmm ? specification ? timing synchronization function (tsf), network allocation vector (nav) maintenance, and target beacon transmission time (tbtt) generation in hardware ? hardware offload for aes-ccmp, legacy wpa? tkip, legacy wep ciphers, and support for key management ? support for coexistence with bluetooth ? (bt) and other external radios ? programmable independent basic service set (ibss) or infrastructure basic service set functionality ? statistics counters for management information base (mib) support mac description the bcm4319 wlan mac is designed to support high throughput operation with low power consumption. in addition, several power saving modes have been implemented that allow the mac to consume very little power while maintaining network wide timing synchronization. the architecture diagram of the mac is shown in figure 14 . the following sections provide an overview of the important mac modules. figure 14: wlan mac architecture embedded cpu interface host registers, dma engines tx-fifo 32 kb wse wep, tkip, aes txe tx a-mpdu rxe pmq psm shared memory 6 kb psm ucode memory ext- ihr ifs backoff, btcx tsf nav ihr bus shm bus mac - phy interface rx-fifo 10 kb rx a-mpdu mac features bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 37 psm the programmable state machine (psm) is a microcode engine that provides most of the low-level hardware control for implementing the 802.11 specification. it is a microcontroller that is highly optimized for flow control operations, which are predominant in implementations of communication protocols. the instruction set and fundamental operations are simple and general, which allows algorithms to be optimized late in the design process. it also allows algorithm changes to track evolving 802.11 specifications. the psm fetches instructions from the microcode memory. it uses shared memory to obtain operands for instructions and to exchange data between both the host and the mac data pipeline (via the shm bus). the psm also uses a scratchpad memory, similar to a register bank, to store frequently accessed and temporary variables. the psm exercises fine grained control over the hardware engines by programming internal hardware registers (ihrs). these ihrs are colocated with the hardware functions they control, and are accessed by the psm via the ihr bus. the psm fetches instructions from the microcode memory using an address determined by the program counter, instruction literal, or a program stack. for arithmetic and logic unit (alu) operations, the operands are obtained from shared memory, scratchpad memory, ihrs, or instruction literals, and the results are written into the shared memory, scratchpad memory, or ihrs. there are two basic branch instructions: conditional branches and alu-based branches. to better support the many decision points in the 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition signals are available to the psm without polling the ihrs) or on the results of alu operations. wse thewireless security engine (wse) encapsulates all the hardware accelerators to perform encryption, decryption, and message integrity check (mic) computation and verification. the accelerators implement the legacy wep, wpa tkip, and wpa2? aes-ccmp cipher algorithms. the psm determines the appropriate cipher algorithm to use based on frame type and association information. it supplies the keys to the hardware engines from an on-chip key table. wse interfaces with the transmit engine (txe) to encrypt and compute the mic on transmit frames and the receive engine (rxe) to decrypt and verify the mic on receive frames. txe the txe constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit frames in the txfifo. it interfaces with the wse module to encrypt frames, and transfers the frames across the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fifos. the mac supports multiple logical queues to support traffic streams that have different quality of service (qos) priority requirements. the psm uses the channel access information from the interframe spacing (ifs) module to schedule a queue from which the next frame is transmitted. once the frame is scheduled, the txe hardware transmits the frame based on a precise timing trigger received from the ifs module. mac features bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 38 the txe module also contains the hardware that allows the rapid assembly of mpdus into an a-mpdu for transmission. the hardware module aggregates the encrypted mpdus by adding appropriate headers and pad delimiters as needed. rxe the rxe constitutes the receive data path of the mac. it interfaces with the dma engine to drain the received frames from the rxfifo. it transfers bytes across the mac-phy interface and interfaces with the wse module to decrypt frames. the decrypted data is stored in the rxfifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteria such as receiver address, bssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the headers of the containers, and disaggregate them into component mpdus. ifs the ifs module contains the timers required to determine interframe space timing including rifs timing. it also contains multiple backoff engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium as indicated by the phy. these timers provide precise timing to the txe to begin frame transmission. the txe uses this information to send response frames or perform transmit frame bursting (rifs or sifs separated, as within a txop). the backoff engines (for each access category) monitor channel activity in each slot duration to determine whether to continue or pause the backoff counters. when the backoff counters reach 0, the txe gets notified so that it may commence frame transmission. in the event that multiple backoff counters decrement to 0 at the same time, the hardware resolves the conflict based on policies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power-save mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep timer, whose count value is initialized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. the mac is restored to its functional state when the timer expires. the psm updates the tsf timer based on the sleep duration, ensuring that the tsf is synchronized to the network. the ifs module also contains the pta hardware that assists the psm in bluetooth coexistence functions. tsf the tsf module maintains the tsf timer of the mac. it also maintains the target beacon transmission time (tbtt). the tsf timer hardware, under the control of the psm, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. the tsf module also generates trigger signals for events that are specified as offsets from the tsf timer, such as uplink and downlink transmission times used in psmp. phy features bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 39 nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the duration field of mac frames. this ensures that the mac complies with the protection mechanisms specified in the standard. the hardware, under the control of the psm, maintains the nav timer and updates the timer appropriately based on received frames. this timing information is provided to the ifs module, which uses it as a virtual carrier- sense indication. mac-phy interface the mac-phy interface consists of a data path interface to exchange rx/tx data from/to the phy. in addition, there is a programming interface that can be controlled either by the host or the psm to configure and control the phy. phy features ? supports ieee 802.11a, 11b, 11g, 11n single stream, and 11j phy standards ? 802.11n single-stream operation in 20 mhz or 40 mhz channels ? supports optional short gi and green field modes in tx and rx. ? supports optional space-time block code (stbc) reception of two space-time streams. ? supports 802.11h/k for worldwide operation ? algorithms achieving low power, enhanced sensitivity, range, and reliability ? automatic gain control scheme for blocking and non-blocking during cellular application scenarios ? closed-loop transmit power control ? digital rf chip calibration algorithms to handle cmos rf chip non-idealities ? on-the-fly channel frequency and transmit power selection ? supports per packet rx antenna diversity ? designed to meet fcc and other regulatory requirements phy description the bcm4319 wlan digital phy is designed to comply with ieee 802.11a/b/g/j/n single stream to provide wlan connectivity supporting data rates from 1 mbps to 72.2 mbps (150 mbps in the 40 mhz channel) for low power, high performance, handheld applications. phy features bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 40 the phy has been designed to work with interference, radio nonlinearity, and impairments. it incorporates efficient implementations of the filters, fast fourier transform (fft), and viterbi-decoder algorithms. efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, and channel estimation and tracking. the phy receiver also contains a robust 11b demodulator. the phy carrier sense has been tuned to provide high throughput for 802.11g/11b hybrid networks with bluetooth coexistence. it has also been designed for shared single antenna systems between wlan and bt to support simultaneous rx-rx. in dual antenna designs, the digital phy has been designed for maximal ratio combining (mrc) in rf. figure 15: wlan phy block diagram the phy is capable of fully calibrating the rf front end to extract the highest performance. on power-up, phy calibrations correct for iq mismatch and local oscillator leakage. phy periodic calibrations compensate for temperature related drift to yield high performance over time. a closed-loop transmit control algorithm maintains the output power to a fixed level with the capability to control tx power on a per packet basis. the phy can receive two spatial streams. the stbc scheme can obtain diversity gains by using multiple transmit antennas at the access point (ap) in a fading channel environment, without increasing the complexity at the station (sta). details of stbc reception are shown in figure 16 on page 41 . filters and radio comp frequency and timing synch carrier sense, agc, and rx fsm radio control block common logic block filters and radio comp afe and radio mac interface buffers ofdm demodulate viterbi decoder tx fsm pa comp modulation and coding modulate/ spread frame and scramble fft/ifft cck/dsss demodulate descramble and deframe coex phy features bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 41 figure 16: stbc receive block diagram in stbc mode, symbols are processed in pairs. equalized output symbols are linearly combined and decoded. channel estimates are refined on every pair of symbols using the received symbols and reconstructed symbols. equalizer demod combine demapper viterbi channel h symbol memory weighted averaging estimate channel transmitter fft of 2 symbols descramble and deframe h old h upd h new wlan 802.11 radio subsystem bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 42 section 7: wlan 802.11 radio subsystem the bcm4319 includes an integrated dual-band wlan rf transceiver that has been optimized to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism or 5 ghz u-nii bands (but not both simultaneously). with its integrated internal transmit power amplifiers, it provides full output power per the ieee 802.11a/b/g/n specifications. support for optional external power amplifiers is also provided. the transmit and receive sections include on-chip filtering, mixing, and gain control functions. figure 17: radio functional block diagram lo generation amp tx i control interface tx q pll lpf rx i lpf rx q mux reference clock lpf lpf mux to baseband from baseband amp 5 ghz rf output 2.4 ghz rf output 5 ghz 2.4 ghz 5 ghz 2.4 ghz lna phase shifter lna phase shifter lna phase shifter lna phase shifter calibration control interface 5 ghz rf input 5 ghz rf input 2.4 ghz rf input 2.4 ghz rf input receiver path bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 43 receiver path the bcm4319 has a wide dynamic range, direct conversion receiver. it employs high order, on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band or the entire 5 ghz u-nii band. the excellent noise figure of the receiver makes an external low-noise amplifier (lna) unnecessary. transmitter path in the transmit path, baseband data is modulated and upconverted to the 2.4 ghz ism or 5 ghz u-nii bands, respectively. the integrated linear on-chip pas are capable of delivering a nominal output power of 20 dbm while meeting the ieee 802.11a and 802.11g specifications. the tx gain has a 32 db range with a resolution of 0.25 db. calibration the bcm4319 features dynamic on-chip calibration, eliminating process variation across components. this enables the bcm4319 to be used in high-volume applications because calibration routines are not required during manufacturing testing. these calibration routines are performed periodically in the course of normal radio operation. an example of this is automatic calibration of the baseband filters for optimum transmit and receive performance. broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 44 pin assignments bcm4319 preliminary data sheet section 8: pin assignments 5.79 mm x 4.58 mm 138-ba ll wlbga package table 4: 5.79 mm x 4.58 mm 138-ball wlbga 1 2 3 4 5 6 7 8 9 10 11 wa wrf_gndpa a_3p3 wrf_gndtx _1p2 wrf_vddtx _1p2 wrf_rfinp_ a1 wrf_vddrx _1p2 wrf_rfinp_ g1 ? wrf_rfinn_ g1_xfmr wrf_gndca b_1p2 xtalin ? wa wb wrf_vddpa a_3p3 wrf_rfout p_a ? wrf_rfinn_ a1_xfmr wrf_gndrx _1p2 ? ? wrf_gndd_ 1p2 wrf_res_e xt ? vddxo wb wc wrf_gndpa a_3p3 wrf_gndpa g_3p3 ? ? wrf_vddlo _1p2 ? wrf_vdda_1 p2 wrf_vddd_ 1p2 wrf_vddpf dcp_1p2 vdd xtalout wc wd wrf_vddpa g_3p3 ??????wrf_gnda_ 1p2 wrf_gndpf dcp_1p2 vss vssxo wd we wrf_rfout p_g wrf_gndpa g_3p3 wrf_afe_pa d_tssi_g wrf_gpio_o ut2 wrf_gndlo _1p2 wrf_vddvc o_1p2 wrf_gndvc o_1p2 wrf_vddca b_1p2 ? xtal_pu sdio_cmd we wf wrf_afe_pa d_test_ip wrf_afe_pa d_test_in wrf_afe_pa d_iqadc_vr ef wrf_gpio_o ut1 vss vddio vdd sdio_data_3 wrf_extre fin wl_reg_on gpio_9 wf wg wrf_afe_pa d_avss_rxa dc wrf_afe_pa d_avdd_rxa dc wrf_afe_pa d_avdd_aux wrf_bbpll_ gnd_1p2 gmode_ext _lna_pu gmode_ext _lna_gain rf_sw_ctrl _n_0 rf_sw_ctrl _p_0 vddio_sd vddio_sd sdio_data_2 wg wh wrf_afe_pa d_test_op wrf_afe_pa d_test_on wrf_afe_pa d_tssi_a wrf_bbpll_ vdd_1p2 tdi tms gmode_tx_ pu rf_sw_ctrl _n_2 rf_sw_ctrl _p_2 gpio_1 sdio_data_1 wh wj amode_tx_p u vddio_rf tck jtag_trst_ l rf_sw_ctrl _n_3 rf_sw_ctrl _p_3 amode_ext_ lna_pu amode_ext_ lna_gain gpio_3 gpio_7 sdio_data_0 wj wk tdo vddio_rf btcx_rf_ac tive vss vdd otp_vdd33 vddio gpio_0 gpio_2 gpio_6 sdio_clk wk wl usb20phy_avd d25_pad usb20phy_avd d12_pad btcx_statu s btcx_freq bt_reg_on wl_reg_on vdd_lnldo2 vout_lnldo 2 sr_testsw g sr_vddbat1 sr_vddbat1 wl wm usb20phy_rref _pad usb20phy_avd d33_pad usb20phy_mo ncdr_pad gpio_8 avss_ldo vref_ldo sr_pnpo sr_pavss sr_avss sr_pvss1 sr_vlx1 wm wn usb20_dev_dp ls usb20phy_agn dpll_pad usb20phy_mo npll_pad uart_tx vdd_cldo vdd_lnldo1 sr_paldo sr_vddbat3 sr_vddbat2 sr_pvss1 sr_vlx1 wn wp usb20_dev_d mns usb20phy_agn d_pad btcx_txcon f uart_rx vout_cldo vout_lnldo 1 sr_paldo sr_vddbat3 sr_avdd2p5 sr_vddnld o sr_vsspldo wp pinout and signal descriptions bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 45 section 9: pinout and signal descriptions signal assignments 138-ball wlbga pinout the 138-ball wlbga pinout is provided in table 5 . bump side view (0,0 center of die) note: the x- and y-coordinate orientation is looking at the silicon face (i.e., looking up at the bottom of the die at the bumps, as opposed to top down). see figure 25 on page 81 for the origin location (0, 0). table 5: wlbga signal assignments by pin number and x- and y-coordinates ball pad signal name x coord y coord wa1 wrf_gndpaa_3p3 ?2654.9 1940 wa10 xtalin ?2654.9 ?1660 wa2 wrf_gndtx_1p2 ?2654.9 1540 wa3 wrf_vddtx_1p2 ?2654.9 1140 wa4 wrf_rfinp_a1 ?2654.9 740 wa5 wrf_vddrx_1p2 ?2654.9 340 wa6 wrf_rfinp_g1 ?2654.9 ?60 wa8 wrf_rfinn_g1_xfmr ?2654.9 ?860 wa9 wrf_gndcab_1p2 ?2654.9 ?1260 wb1 wrf_vddpaa_3p3 ?2254.9 1940 wb11 vddxo ?2254.9 ?2060 wb2 wrf_rfoutp_a ?2254.9 1540 wb4 wrf_rfinn_a1_xfmr ?2254.9 740 wb5 wrf_gndrx_1p2 ?2254.9 340 wb8 wrf_gndd_1p2 ?2254.9 ?860 wb9 wrf_res_ext ?2254.9 ?1260 wc1 wrf_gndpaa_3p3 ?1854.9 1940 wc10 vdd ?1854.9 ?1660 wc11 xtalout ?1854.9 ?2060 wc2 wrf_gndpag_3p3 ?1854.9 1540 wc5 wrf_vddlo_1p2 ?1854.9 340 wc7 wrf_vdda_1p2 ?1854.9 ?460 wc8 wrf_vddd_1p2 ?1854.9 ?860 signal assignments bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 46 wc9 wrf_vddpfdcp_1p2 ?1854.9 ?1260 wd1 wrf_vddpag_3p3 ?1454.9 1940 wd10 vss ?1454.9 ?1660 wd11 vssxo ?1454.9 ?2060 wd8 wrf_gnda_1p2 ?1454.9 ?860 wd9 wrf_gndpfdcp_1p2 ?1454.9 ?1260 we1 wrf_rfoutp_g ?1054.9 1940 we10 xtal_pu ?1054.9 ?1660 we11 sdio_cmd ?1054.9 ?2060 we2 wrf_gndpag_3p3 ?1054.9 1540 we3 wrf_afe_pad_tssi_g ?1054.9 1140 we4 wrf_gpio_out2 ?1054.9 740 we5 wrf_gndlo_1p2 ?1054.9 340 we6 wrf_vddvco_1p2 ?1054.9 ?60 we7 wrf_gndvco_1p2 ?1054.9 ?460 we8 wrf_vddcab_1p2 ?1054.9 ?860 wf1 wrf_afe_pad_test_ip ?654.9 1940 wf10 wl_reg_on ?654.9 ?1660 wf11 gpio_9 ?654.9 ?2060 wf2 wrf_afe_pad_test_in ?654.9 1540 wf3 wrf_afe_pad_iqadc_vref ?654.9 1140 wf4 wrf_gpio_out1 ?654.9 740 wf5 vss ?654.9 340 wf6 vddio ?654.9 ?60 wf7 vdd ?654.9 ?460 wf8 sdio_data_3 ?654.9 ?860 wf9 wrf_extrefin ?654.9 ?1260 wg1 wrf_afe_pad_avss_rxadc ?254.9 1940 wg10 vddio_sd ?254.9 ?1660 wg11 sdio_data_2 ?254.9 ?2060 wg2 wrf_afe_pad_avdd_rxadc ?254.9 1540 wg3 wrf_afe_pad_avdd_aux ?254.9 1140 wg4 wrf_bbpll_gnd_1p2 ?254.9 740 wg5 gmode_ext_lna_pu ?254.9 340 wg6 gmode_ext_lna_gain ?254.9 ?60 wg7 rf_sw_ctrl_n_0 ?254.9 ?460 wg8 rf_sw_ctrl_p_0 ?254.9 ?860 wg9 vddio_sd ?254.9 ?1260 wh1 wrf_afe_pad_test_op 145.1 1940 table 5: wlbga signal assignments by pin number and x- and y-coordinates (cont.) ball pad signal name x coord y coord signal assignments bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 47 wh10 gpio_1 145.1 ?1660 wh11 sdio_data_1 145.1 ?2060 wh2 wrf_afe_pad_test_on 145.1 1540 wh3 wrf_afe_pad_tssi_a 145.1 1140 wh4 wrf_bbpll_vdd_1p2 145.1 740 wh5 tdi 145.1 340 wh6 tms 145.1 ?60 wh7 gmode_tx_pu 145.1 ?460 wh8 rf_sw_ctrl_n_2 145.1 ?860 wh9 rf_sw_ctrl_p_2 145.1 ?1260 wj1 amode_tx_pu 545.1 1940 wj10 gpio_7 545.1 ?1660 wj11 sdio_data_0 545.1 ?2060 wj2 vddio_rf 545.1 1540 wj3 tck 545.1 1140 wj4 jtag_trst_l 545.1 740 wj5 rf_sw_ctrl_n_3 545.1 340 wj6 rf_sw_ctrl_p_3 545.1 ?60 wj7 amode_ext_lna_pu 545.1 ?460 wj8 amode_ext_lna_gain 545.1 ?860 wj9 gpio_3 545.1 ?1260 wk1 tdo 945.1 1940 wk10 gpio_6 945.1 ?1660 wk11 sdio_clk 945.1 ?2060 wk2 vddio_rf 945.1 1540 wk3 btcx_rf_active 945.1 1140 wk4 vss 945.1 740 wk5 vdd 945.1 340 wk6 otp_vdd33 945.1 ?60 wk7 vddio 945.1 ?460 wk8 gpio_0 945.1 ?860 wk9 gpio_2 945.1 ?1260 wl1 usb20phy_avdd25_pad 1345.1 1940 wl10 sr_vddbat1 1345.1 ?1660 wl11 sr_vddbat1 1345.1 ?2060 wl2 usb20phy_avdd12_pad 1345.1 1540 wl3 btcx_status 1345.1 1140 wl4 btcx_freq 1345.1 740 wl5 bt_reg_on 1345.1 340 table 5: wlbga signal assignments by pin number and x- and y-coordinates (cont.) ball pad signal name x coord y coord signal assignments bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 48 wl6 wl_reg_on 1345.1 ?60 wl7 vdd_lnldo2 1345.1 ?460 wl8 vout_lnldo2 1345.1 ?860 wl9 sr_testswg 1345.1 ?1260 wm1 usb20phy_rref_pad 1745.1 1940 wm10 sr_pvss1 1745.1 ?1660 wm11 sr_vlx1 1745.1 ?2060 wm2 usb20phy_avdd33_pad 1745.1 1540 wm3 usb20phy_moncdr_pad 1745.1 1140 wm4 gpio_8 1745.1 740 wm5 avss_ldo 1745.1 340 wm6 vref_ldo 1745.1 ?60 wm7 sr_pnpo 1745.1 ?460 wm8 sr_pavss 1745.1 ?860 wm9 sr_avss 1745.1 ?1260 wn1 usb20_dev_dpls 2145.1 1940 wn10 sr_pvss1 2145.1 ?1660 wn11 sr_vlx1 2145.1 ?2060 wn2 usb20phy_gndpll_pad 2145.1 1540 wn3 usb20phy_monpll_pad 2145.1 1140 wn4 uart_tx 2145.1 740 wn5 vdd_cldo 2145.1 340 wn6 vdd_lnldo1 2145.1 ?60 wn7 sr_paldo 2145.1 ?460 wn8 sr_vddbat3 2145.1 ?860 wn9 sr_vddbat2 2145.1 ?1260 wp1 usb20_dev_dmns 2545.1 1940 wp10 sr_vddnldo 2545.1 ?1660 wp11 sr_vsspldo 2545.1 ?2060 wp2 usb20phy_agnd_pad 2545.1 1540 wp3 btcx_txconf 2545.1 1140 wp4 uart_rx 2545.1 740 wp5 vout_cldo 2545.1 340 wp6 vout_lnldo1 2545.1 ?60 wp7 sr_paldo 2545.1 ?460 wp8 sr_vddbat3 2545.1 ?860 wp9 sr_avdd2p5 2545.1 ?1260 table 5: wlbga signal assignments by pin number and x- and y-coordinates (cont.) ball pad signal name x coord y coord signal descriptions bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 49 signal descriptions 138-ball wlbga package signal descriptions for the 138-ball wlbga are provided in table 6 . *see table 7: ?sdio pin descriptions,? on page 54 for additional information. note: digital ios are not failsafe. other devices should not drive bcm4319 lines when the corresponding io supply is absent. if such a requirement exists in the system, add a series resistor greater than 3.9 k on the line. note: internal pulls on digital ios are active only when vddc and the corresponding io supply are present. note: xtalin is failsafe. table 6: 138-ball wlbga signal descriptions ball signal name type description rf interface we1 wrf_rfoutp_g o 802.11g internal power amplifier rf output wa6 wrf_rfinp_g1 i 802.11g rx rf input (50 ) wa8 wrf_rfinn_g1_xfmr o 802.11g rx transformer rf ground we3 wrf_afe_pad_tssi_g i transmit signal strength indicator for optional external 802.11g power amplifier. leave nc if not used. wb2 wrf_rfoutp_a o 802.11a internal power amplifier rf output. wa4 wrf_rfinp_a1 i 802.11a rx rf input (50 ) wb4 wrf_rfinn_a1_xfmr i 802.11a rx transformer rf ground wh3 wrf_afe_pad_tssi_a i transmit signal strength indicator for optional external 802.11a power amplifier. leave nc if not used. wb9 wrf_res_ext o connect to external 15 k (1% tolerance) resistor to ground. rf control lines (io supply = vddio_rf) wg8 rf_sw_ctrl_p_0 o programmable rf switch control lines: default = low. wg7 rf_sw_ctrl_n_0 o wh9 rf_sw_ctrl_p_2 o wh8 rf_sw_ctrl_n_2 o wj6 rf_sw_ctrl_p_3 o programmable rf switch control line: default = high. wj5 rf_sw_ctrl_n_3 o programmable rf switch control line: default = low. wh7 gmode_tx_pu o 802.11g optional external pa control wg5 gmode_ext_lna_pu o enable signal for optional external 802.11g lna wg6 gmode_ext_lna_gain o control signal for optional external 802.11g lna wj1 amode_tx_pu o 802.11a optional external pa control signal descriptions bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 50 wj7 amode_ext_lna_pu o enable signal for optional external 802.11a lna. wj8 amode_ext_lna_gain o control signal for optional external 802.11a lna. integrated ldos wn5 vdd_cldo i input supply pin for cldo: also functions as the feedback pin for the cbuck switching regulator wn6 vdd_lnldo1 i input supply pin for lnldo1 wl7 vdd_lnldo2 i input supply pin for lnldo2 (backup linear regulator) wp5 vout_cldo o 1.2v output for core ldo, 200 ma wp6 vout_lnldo1 o 1.2v output for low noise lnldo1, 150 ma wl8 vout_lnldo2 o 1.2v or 2.5v?3.1v programmable output for low noise lnldo2, 50 ma wm6 vref_ldo o vref bypass: connect external decoupling capacitor to ground. wp9 sr_avdd2p5 o 2.5v ldo2p5 output: used for various internal bcm4319 blocks in addition to the usb phy: the output capacitor is required even when usb functionality is not used. wn7 sr_paldo o internal paldo output or feedback of output from external pnp wp7 sr_paldo o wm7 sr_pnpo o control output for pnp base wl9 sr_testswg o test output for switcher/ldos wn8 sr_vddbat3 i battery supply input for paldo wp8 sr_vddbat3 i wp10 sr_vddnldo o nldo reference pin output: connect to 220 nf external capacitor to ground. do not use for other external circuits. integrated switching regulator wl10 sr_vddbat1 i core buck regulator: battery voltage input wl11 sr_vddbat1 i wn9 sr_vddbat2 i wm11 sr_vlx1 o core buck regulator: output to inductor ? wn11 sr_vlx1 o wp11 sr_vsspldo i tracks battery voltage: connect to 220 nf external capacitor to battery. sdio bus interface* (io supply = vddio_sd) we11 sdio_cmd i/o sdio command line wj11 sdio_data_0 i/o sdio data line 0 wh11 sdio_data_1 i/o sdio data line 1 wg11 sdio_data_2 i/o sdio data line 2 wf8 sdio_data_3 i/o sdio data line 3 wk11 sdio_clk i/o sdio clock table 6: 138-ball wlbga signal descriptions (cont.) ball signal name type description signal descriptions bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 51 usb 2.0 interface wn1 usb20_dev_dpls i/o usb port data plus wp1 usb20_dev_dmns i/o usb port data minus wm1 usb20phy_rref_pad i/o usb phy bandgap reference resistor. connect to ground via a 4.02k resistor in parallel with a 100 pf capacitor. wm3 usb20phy_moncdr_pad i/o usb cdr monitor (reserved for testing) wn3 usb_monpll i/o usb phy pll monitor (reserved for testing) uart interface (io supply = vddio) wp4 uart_rx i serial output for uart. connect to rs-232 dte for exchanging data with other serial devices. this signal has an internal pull-up resistor (approximately 60k ohms) and can be left unconnected (nc) if not used. wn4 uart_tx o serial input for uart. connect to rs-232 dte for exchanging data with other serial devices. if not used, it may be left unconnected. external coexistence interface (io supply = vddio) wl4 btcx_freq i indicates that the coexistent bt is about to transmit on a restricted channel: internal pull-down. wk3 btcx_rf_active i indicates that the coexistent bt is active: internal pull- down. wl3 btcx_status i indicates the coexistent bt priority status and rx/tx direction. wp3 btcx_txconf o output permission for the coexistent bt to transmit. jtag interface (io supply = vddio_rf) (for testing only) wh6 tms i for normal operation, connect as described in the jtag specification (ieee std 1149.1). otherwise, if jtag is not used, these pins can be left unconnected (nc) as they have internal pull-up resistors (approximately 60k ohms). wk1 tdo o wh5 tdi i wj3 tck i wj4 jtag_trst_l i gpio interface (io supply = vddio, programmable pulls) wk8 gpio_0 i/o general-purpose interface pins. wh10 gpio_1 i/o wk9 gpio_2 i/o wj9 gpio_3 i/o wk10 gpio_6 i/o wj10 gpio_7 i/o wm4 gpio_8 i/o wf11 gpio_9 i/o table 6: 138-ball wlbga signal descriptions (cont.) ball signal name type description signal descriptions bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 52 miscellaneous signals wl6 wl_reg_on i used by pmu to enable/disable power the internal regulators. vih = 1.6v, maximum = 3.6v, internal pull-down 200 kohm. analog input pin. wa10 xtalin i crystal oscillator input wc11 xtalout o crystal oscillator output we10 xtal_pu o request signal to host to provide reference clock. the bcm4319 asserts this signal when the reference clock (e.g., tcxo) should be enabled. statextal_pu xtal clock neededhigh xtal clock not needed60 k internal pull-down add a external pull-down (100 k ) to keep the signal deasserted when the bcm4319 is powered down. io supply = vddio wf10 ext_por_l i low asserting global chip reset: digital input pin. io supply = vddio radio and baseband power supplies wd1 wrf_vddpag_3p3 i 3.3v for the internal power amplifiers wb1 wrf_vddpaa_3p3 i 3.3v for the internal power amplifiers we6 wrf_vddvco_1p2 i 1.2v supply for pll wa3 wrf_vddtx_1p2 i 1.2v supply for radio transmit section wa5 wrf_vddrx_1p2 i 1.2v supply for radio receive section wc9 wrf_vddpfdcp_1p2 i 1.2v supply for pll wc5 wrf_vddlo_1p2 i 1.2v supply for lo generator wc8 wrf_vddd_1p2 i 1.2v supply for pll we8 wrf_vddcab_1p2 i 1.2v supply for cab wc7 wrf_vdda_1p2 i 1.2v supply for pll wh4 wrf_bbpll_vdd_1p2 i 1.2v supply for baseband pll wg2 wrf_afe_pad_avdd_rxa dc i 1.2v filtered supply for adc wg3 wrf_afe_pad_avdd_aux i 1.2v filtered supply for afe aux table 6: 138-ball wlbga signal descriptions (cont.) ball signal name type description signal descriptions bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 53 miscellaneous power supplies wg9 vddio_sd i sdio i/o supply (1.8v to 3.3v) vddio_sd should be supplied externally if the sdio interface is used. even if the sdio interface is not used, vddio_sd should not be grounded (instead, the paldo output can be used for vddio_sd. alternately vddio_sd can use the same supply as vddio). wg10 vddio_sd i wj2 vddio_rf i rf i/o supply (2.6v to 3.3v) vddio_rf should be supplied externally (it cannot be supplied from the paldo) when the rf front-end is shared with other devices, such as bluetooth. the same external supply should be used for pulls-ups, because paldo is shutdown during sleep mode and when the bcm4319 is powered down. wk2 vddio_rf i wf6 vddio i digital i/o supply (1.8v to 3.3v) vddio should be supplied externally wk7 vddio i wc10 vdd i 1.2v digital core supply wf7 vdd i wk5 vdd i wb11 vddxo i 1.2v crystal oscillator filtered power supply wk6 otp_vdd33 i 3.3v otp power supply (no lower than 3.0v) wl1 usb20phy_avdd25_pad i usb phy analog 2.5v supply wl2 usb20phy_avdd12_pad i usb phy core 1.2v supply wm2 usb20phy_avdd33_pad i usb phy analog 3.3v supply ground wd10 vss ? digital ground wf5 wk4 wm5 avss_ldo ? ground wd11 vssxo ? crystal oscillator ground wn10 sr_pvss1 ? ground wm10 sr_pvss1 ? ground wm8 sr_pavss ? ground wm9 sr_avss ? ground wa1 wrf_gndpaa_3p3 ? ground wa2 wrf_gndtx_1p2 ? ground wa9 wrf_gndcab_1p2 ? ground wb5 wrf_gndrx_1p2 ? ground wb8 wrf_gndd_1p2 ? ground wc1 wrf_gndpaa_3p3 ? ground wc2 wrf_gndpag_3p3 ? ground table 6: 138-ball wlbga signal descriptions (cont.) ball signal name type description sdio pin descriptions bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 54 sdio pin descriptions wd8 wrf_gnda_1p2 ? ground wd9 wrf_gndpfdcp_1p2 ? ground we2 wrf_gndpag_3p3 ? ground we5 wrf_gndlo_1p2 ? ground we7 wrf_gndvco_1p2 ? ground wg1 wrf_afe_pad_avss_rxa dc ? ground wg4 wrf_bbpll_gnd_1p2 ? ground wl5 bt_reg_on ? ground wp2 usb20phy_agnd_pad ? ground wn2 usb20phy_gndpll_pad ? ground no connect we4 wrf_gpio_out2 o no connect wf1 wrf_afe_pad_test_ip i no connect wf2 wrf_afe_pad_test_in i no connect wf3 wrf_afe_pad_iqadc_vr ef o no connect wf4 wrf_gpio_out1 o no connect wf9 wrf_extrefin i no connect wh1 wrf_afe_pad_test_op o no connect wh2 wrf_afe_pad_test_on o no connect table 7: sdio pin descriptions sd 4-bit mode sd 1-bit mode gspi mode sdio_data_0 data line 0 data data line do data output sdio_data_1 data line 1 or interrupt irq interrupt irq interrupt sdio_data_2 data line 2 or read wait rw read wait nc not used sdio_data_3 data line 3 n/c not used cs card select sdio_clk clock clk clock sclk clock sdio_cmd command line cmd command line di data input table 6: 138-ball wlbga signal descriptions (cont.) ball signal name type description strapping options and gpio functions bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 55 figure 18: signal connections to sdio card (sd 4-bit mode) figure 19: signal connections to sdio card (gspi mode) strapping options and gpio functions the pins listed in table 8 on page 56 are sampled at power-on reset (por) after wl_reg_on goes high, to determine the various operating modes. sampling occurs within 150 milliseconds after wl_reg_on goes high. after por each pin assumes the gpio or alternative function specified in the signal descriptions table. each pin has an programmable internal pull-up or pull-down resistor that determines the default mode. to change the mode, connect an external pull-up resistor to vddio or a pull-down resistor to gnd?use a 10 k resistor or less (refer to the reference board schematics for more information). all gpios can be safely used in output mode. gpios that do not have interfering strapping options can be safely used as input pins, specifically including: ? usb mode: 1, 2, and 3 ? sdio mode: 1, 2, 3, and 9 ? gspi mode: 2 and 9 sd host bcm4319 clk cmd dat(3:0) 47k (see note) note: section 6 of the sdio physical layer specification specifies that the sdio host must provide a 10k - 100k ohm pull-up resistor on each cmd and dat(3:0) signal line. this requirement must be met to properly operate the bcm4319. 47k x4 (see note) vddio_sd sd host bcm4319 sclk di do irq cs strapping options and gpio functions bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 56 table 8: strapping options pin name ball # default state function description gpio_0 wk8 low selects interface modes a (depends on strapping). this pin should not be used as a generic input and should not be driven by other devices. a. typically used as an output for wlan_host_wake and as an out-of-band interrupt for the sdio interface. it has a hardware generated interrupt and is always valid (unlike the sdio in-band interrupt, which is valid only when data is not driven on the sdio lines). this out-of-band interrupt mimics the final in-band interrupts so all of the interrupt enables (such as per-function interrupt enables) should be set appropriately. ? usb mode ( strapping): ? 0: normal (default) ? 1: usb cpu-less mode sdio mode ( strapping): ? 0: sdio (default) ?1: gspi mode gpio_1 wh10 low gpio ? gspi clock polarity strapping in gspi mode: do not care in all other modes b . default = 0 b. this pin is often used as an input for the out-of-band power control signal wlan_wake. gpio_2 wk9 ? gpio ? no strapping functions for this pin gpio_3 wj9 low gpio ? gspi clock phase strapping in gspi mode: do not care in all other modes. gpio_6 gpio_7 wk10 wj10 low high gpio[7:6] [7:6] = 00 otp enabled, use default sdio cis [7:6] = 01 01 reserved [7:6] = 10 otp enabled, load sdio cis from otp (default) [7:6] = 11 11 reserved gpio_8 wm4 low sets sdio and usb 0 usb mode (default) 1sdio mode gpio_9 wf11 high boot mode ? usb mode: usb normal mode 0: remap to ram, arm held in reset after por (internal use only) 1: boot from rom, arm automatically runs after por (required for usb normal mode) usb cpu-less mode: do not care, arm held in reset after por sdio/gspi mode do not care, arm held in reset after por operating conditions bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 57 section 10: operating conditions environmental ratings absolute maximum ratings these specifications indicate levels where permanent damage to the device can occur. functional operation is not guaranteed under these conditions. operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. note: values in this data sheet are design goals and are subject to change based on the results of device characterization. table 9: environmental characteristics characteristic value units conditions/comments ambient temperature (t a ) ?30 to +85 a a. the bcm4319 supports a functional operating range of ?30 to +85 c. however, the optimal rf performance specified in this datasheet is only guaranteed for temperatures from ?10 to +55 c. coperation storage temperature ?40 to +105 c? relative humidity less than 60 % storage less than 85 % operation esd + 2 kv human body model table 10: absolute maximum ratings rating symbol value unit dc supply voltage for vbat vbat ?0.5 to +6.5 v dc supply voltage for i/o vddo a a. vddo = vddio/vddio_sd/vddio_rf ?0.5 to +4.1 v dc supply voltage for rf vddrf ?0.5 to +1.32 v dc supply voltage for core vddc ?0.5 to +1.32 v maximum undershoot voltage for i/o vundershoot ?0.5 v maximum junction temperature t j 125 c recommended operating conditions and dc characteristics bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 58 recommended operating conditi ons and dc characteristics table 11: recommended operating conditions and dc characteristics element symbol value unit minimum typical maximum dc supply voltage for vbat a a. functional operation is not guaranteed outside these limits, and operation outside these limits for extended periods can adversely affect long-term reliability of the device. ? 2.7 b b. the bcm4319 is functional across this range of voltages. however, optimal rf performance specified in the datasheet is only guaranteed while vbat is between 3.0 and 5.25v. ?5.5 b v dc supply voltage for otp, usb a ? 3.0 3.3 3.63 v dc supply voltage for pa a ? 2.8 c c. with vbat = 3.0v paldo output = 3.0 ?0.2 (dropout voltage) = 2.8v 3.3 3.63 v dc supply voltage for i/o a, d d. the supported voltage range applies to all three i/o supplies: vddio, vddio_sd, and vddio_rf. vddio and vddio_sd often use 1.8v signaling; however, vddio_rf tends to use a higher voltage rail, such as 3.3v, because this supply rail is used for the bcm4319 rf switch and front-end control lines. rf front-end components (such as transmit/receive switches) tend to require higher control voltages. vddo 1.62 3.3 or 1.8 3.63 v dc supply voltage for core a vddc 1.176 1.225 1.30 v 1.2v analog (radio/afe/pll/xtal/usb 1.2) a ? 1.176 1.225 1.30 v 2.5v usb a ? 2.25 2.5 2.75 v input low voltage (vddo = 3.3v) e e. for any other vddo from 1.8v to 3.3v (10%), v ih and v il are specified as v ih = from 0.7 * vddo to vddo and v il = from 0v to 0.2 * vddo. v il ??0.8v input high voltage (vddo = 3.3v) e v ih 2.0 ? vddo v input low voltage (vddo = 1.8v) e v il ??0.6v input high voltage (vddo = 1.8v) e v ih 1.1 ? vddo v input high voltage (wl_reg_on pin) v ih 1.6 ? 3.6 v output low voltage (iol = 100 a) v ol ??0.2v output high voltage (ioh = ?100 a) v oh vddo ? 0.2v ? ? v input low current i il ?0.3 ? a input high current i ih ?0.3 ? a output low current (vddio/vddio_rf) i ol ??3.0ma output high current (vddio/vddio_rf) i oh ??3.0ma output low current (vddio_sd) i ol ? ? programmable: 2 to 12 ma (default 10 ma) ma output high current (vddio_sd) i oh ?? ma recommended operating conditions and dc characteristics bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 59 current consumption table 12: current consumption operational state vbat=3.6v, vddio = 3.3v , 25c sdio typical usb typical off (wl_reg_on = low) a a. all measurements include vddio current. depending on factors such as the power topology, external pu/pd resistors, etc., additional leakage current may occur at the board level. 16 ua 450 ua b b. assumes vbat is directly used for usb 3.3v supply sleep 180 ua 41 ma c c. usb interface remains in active mode idle between beacons 180 ua 41 ma c ieee ps @ dtim = 100 ms d d. beacon interval = 102.4 ms, dtim = 1 or 3, beacon duration = 1 ms @ 1 mbps = 192 s phy header + 808 us (101 byte) mpdu 1.25 ma 43 ma c ieee ps @ dtim = 300 ms d 550 ua 42 ma c beacon reception 71 ma 103 ma rx listen 65 ma 97 ma rx 1 mbps 71 ma 103 ma rx 11 mbps 71 ma 103 ma rx 6 mbps 72 ma 103 ma rx 54 mbps 76 ma 107 ma rx mcs0 20 mhz channel 72 ma 103 ma rx mcs7 20 mhz channel 77 ma 108 ma rx listen 40 mhz channel 77 ma 108 ma rx mcs0 40 mhz channel 82 ma 113 ma rx mcs7 40 mhz channel 87 ma 118 ma tx rate tx power at chipout e e. chip tx output power is based on broadcom reference board measurements and backward calculation from antenna test port. ?? tx cck 20 dbm 320 ma 355 ma tx ofdm bpsk 19 dbm 305 ma 340 ma tx ofdm qpsk 19 dbm 305 ma 340 ma tx ofdm 16 qam 18 dbm 290 ma 325 ma tx ofdm 64 qam 18 dbm 290 ma 325 ma tx mcs0 20 mhz channel 16 dbm 275 ma 310 ma tx mcs7 20 mhz channel 16 dbm 270 ma 305 ma tx mcs0 40 mhz channel 16 dbm 290 ma 325 ma tx mcs7 40 mhz channel 16 dbm 285 ma 320 ma wlan rf specifications bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 60 section 11: wlan rf specifications introduction the bcm4319 includes an integrated dual-band direct conversion radio that supports either the 2.4 ghz ieee 802.11g band or the 5 ghz ieee 802.11a band. the bcm4319 does not provide simultaneous 2.4 ghz and 5 ghz operation. this section describes the rf characteristics of the 2.4 ghz and 5 ghz sections of the radio. typical values apply for vbat = 3.6v and ambient temperature = 25c. figure 20: rf port location 2.4 ghz band general rf specifications note: unless otherwise stated, these specifications apply over the range of operating conditions specified in ta b le 9 , and table 10 on page 57 , and table 11 on page 58 . outside these limits, functional operation is not guaranteed. table 13: 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? 5 10 s rx/tx switch time including tx ramp up ? 5 5 s power up / down ramp time dsss/cck modulations ? ? < 2 s bcm4219 rf switch (0.5 db insertion loss) wlan tx wlan rx filter antenna port rf port chipout 2.4 ghz band receiver rf specifications bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 61 2.4 ghz band receiver rf specifications table 14: 2.4 ghz band receiver rf specifications parameter condition/notes min typ a max unit out-of-band blocking performance. the blocking level at the wlan rf port for 1 db rx sensitivity degradation (without external filtering) 776?794 mhz (cdma2000) ?8 dbm ? ? dbm 824?849 mhz (cdmaone) ?24.5 ? ? dbm 824?849 mhz (gsm850) b ?16.5 ? ? dbm 880?915 mhz (e-gsm) ?2??dbm 1710?1785 mhz (gsm1800) ?17 ? ? dbm 1850?1910 mhz (gsm1800) ?21 ? ? dbm 1850?1910 mhz (cdmaone) ?32 ? ? dbm 1850?1910 mhz (wcdma) ?29 ? ? dbm 1920?1980 mhz (wcdma) ?32 ? ? dbm rx sensitivity (8% per for 1024 octet psdu) at wlan rf port c 1 mbps dsss ?94 ?97 ? dbm 2 mbps dsss ?91 ?94 ? dbm 5.5 mbps dsss ?90 ?92 ? dbm 11 mbps dsss ?88 ?90 ? dbm rx sensitivity (10% per for 1024 octet psdu) at wlan rf port a 6 mbps ofdm ?89.5 ?91.5 ? dbm 9 mbps ofdm ?89 ?90.5 ? dbm 12 mbps ofdm ?88 ?90 ? dbm 18 mbps ofdm ?86 ?88 ? dbm 24 mbps ofdm ?84 ?86 ? dbm 36 mbps ofdm ?80 ?82 ? dbm 48 mbps ofdm ?76 ?78 ? dbm 54 mbps ofdm ?74 ?76 ? dbm 2.4 ghz band receiver rf specifications bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 62 rx sensitivity (10% per for 4096 octet psdu) at wlan rf port a,d. defined for default parameters: gf, 800 ns gi, and non-stbc. 20 mhz channel spacing for all mcs rates mcs 7 ?71 ?73 ? dbm mcs 6 ?72.5 ?74.5 ? dbm mcs 5 ?74.5 ?76.5 ? dbm mcs 4 ?78.5 ?80.5 ? dbm mcs 3 ?82 ?84 ? dbm mcs 2 ?84.5 ?86.5 ? dbm mcs 1 ?86.5 ?88.5 ? dbm mcs 0 ?88 ?90 ? dbm 40 mhz channel spacing for all mcs rates mcs 7 ?67.5 ?69.5 ? dbm mcs 6 ?69.0 ?71.0 ? dbm mcs 5 ?70.5 ?72.5 ? dbm mcs 4 ?74.5 ?76.5 ? dbm mcs 3 ?77.0 ?79.0 ? dbm mcs 2 ?80.0 ?82.0 ? dbm mcs 1 ?82.5 ?84.5 ? dbm mcs 0 ?85.0 ?87.0 ? dbm in-band static cw jammer immunity (fc ? 8 mhz < fcw + 8 mhz) rx per < 1%, 54 mbps ofdm, 1000 octet psdu for: (rxsens + 23 db < rxlevel < max input level) ?80 ? ? dbm maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?3.5??dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?9.5??dbm @ 6?54 mbps (10% per, 1024 octets) ?9.5??dbm @ mcs0?7 rates (10% per, 4095 octets) ?9.5??dbm adjacent channel rejection-dsss (difference between interfering and desired signal at 8% per for 1024 octet psdu with desired signal level as specified in condition/ notes) desired and interfering signal 30 mhz apart 1 mbps dsss ?74 dbm 35 ? ? db 2 mbps dsss ?74 dbm 35 ? ? db desired and interfering signal 25 mhz apart 5.5 mbps dsss ?70 dbm 35 ? ? db 11 mbps dsss ?70 dbm 35 ? ? db table 14: 2.4 ghz band receiver rf specifications (cont.) parameter condition/notes min typ a max unit 2.4 ghz band receiver rf specifications bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 63 adjacent channel rejection-ofdm (difference between interfering and desired signal (25 mhz apart) at 10% per for 1024 octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db adjacent channel rejection mcs0? 7 (difference between interfering and desired signal (25 mhz apart) at 10% per for 4096 octet psdu with desired signal level as specified in condition/notes) mcs7 ?61 dbm ?2 ? ? db mcs6 ?62 dbm ?1 ? ? db mcs5 ?63 dbm 0 ? ? db mcs4 ?67 dbm 4 ? ? db mcs3 ?71 dbm 8 ? ? db mcs2 ?74 dbm 11 ? ? db mcs1 ?76 dbm 13 ? ? db mcs0 ?79 dbm 16 ? ? db maximum receiver gain ? ? ? 105 ? db gain control step ? ??3?db rssi accuracy e range ?98 dbm to ?30 dbm ?5?5db range above ?30 dbm ?8?8db a. values are measured at the input of the bcm4319. thus, they include insertion losses from the integrated baluns, but exclude losses from the external circuits. b. the blocking levels are valid for channels 1 through 11. (for higher channels, the performance may be lower due to third harmonic signals (3 824 mhz) falling within band.) c. derate by 1.5 db for ?30 c to ?10c and 55c to 85c. d. sensitivity degradations for alternate settings in mcs modes. mm: 0.5 db drop, sgi: 2 db drop, and stbc: 0.75 db drop. e. the minimum and maximum values shown have 95% confidence table 14: 2.4 ghz band receiver rf specifications (cont.) parameter condition/notes min typ a max unit 2.4 ghz band transmitter rf specifications bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 64 2.4 ghz band transmi tter rf specifications table 15: 2.4 ghz band transmitter rf specifications characteristic condition min typ max unit rf output frequency range ? 2400 ? 2500 mhz tx power at chipout for highest power level setting at 25c, vbat = 3.6v and spectral mask and evm compliance a b a. derate by 1.5 db for ?30c to ?10c, and 55c to 85c. cck 18.5 20 21.5 dbm ofdm bpsk 17.5 19 20.5 dbm ofdm qpsk 17.5 19 20.5 dbm ofdm 16 qam 16.5 18 19.5 dbm ofdm 64 qam 16.5 18 19.5 dbm mcs0 to mcs7 20 mhz channels 14.5 16 17.5 dbm mcs0 to mcs7 40 mhz channels 14.5 16 17.5 dbm gain flatness maximum gain ??2db output ip3 maximum gain ?37 ?dbm output p1db ? ?27 ?dbm carrier suppression ? 15 ? ? dbr cck tx spectrum mask @ max gain fc ? 22 mhz < f < fc ? 11 mhz ? ? ?30 dbr fc + 11 mhz < f< fc + 22 mhz ? ? ?30 dbr f < fc ? 22 mhz; and f > fc + 22 mhz ? ? ?50 dbr ofdm tx spectrum mask (chip output power = 16 dbm) f < fc ? 11 mhz and f > fc + 11 mhz ? ? ?26 dbc f < fc ? 20 mhz and f > fc + 20 mhz ? ? ?35 dbr f < fc ? 30 mhz and f > fc + 30 mhz ? ? ?40 dbr tx modulation accuracy (i.e. evm) at maximum gain ieee 802.11b mode ??35%? ieee 802.11g mode qam64 54 mbps ??5%? gain control step size ? ? 0.25 db ? db/step amplitude balance c dc input ?1 ? 1 db phase balance a dc input ?1.5 ? 1.5 baseband differential input voltage shaped pulse ?0.6 ?vpp tx power ramp up 90% of final power ??2 sec tx power ramp down 10% of final power ??2 sec tx power control dynamic range ? 10 ? ? db closed-loop tx power variation across full temperature and voltage range. power accuracy of 1.5 db for 10?20 dbm and 3 db for 5?10 dbm. ??1.5db carrier suppression ? 15 ? ? dbc gain control step ? ?.25 ? db see next page for additional footnotes. 2.4 ghz band local oscillator specifications bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 65 2.4 ghz band local osci llator specifications b. powers shown are at chipout. measurements taken at the antenna port are lower due to insertion losses of the external rf front end, including any rf switches or filters. front end insertion losses are system-design dependent. the wlan driver power-control algorithm keeps the output power within +/- 1.5 db of the values specified in nvram. output power can vary, depending on target output power and modulation offset settings in the nvram file. values shown assume the following nvram variable settings: pa0maxpwr = 82 cckpo = 0 ofdmpo = 0x44442222 mcs2gpo0 = 0x8888 mcs2gpo1 = 0x8888 mcs2gpo4 = 0x8888 mcs2gpo5 = 0x8888 in this case an insertion loss of 1 db is assumed between the output and the antenna port. c. at 3 mhz offset from the carrier frequency. table 16: 2.4 ghz band local oscillator specifications characteristic condition minimum typical maximum unit vco frequency range ? 2412 ? 2484 mhz reference input frequency range ? ? various a a. reference supported frequencies range from 12 mhz to 52 mhz. ?mhz reference spurs ? ? ? ?34 dbc local oscillator phase noise, single-sided from 1?300 khz offset ????86.5dbc/hz clock frequency tolerance ? ? ? 20 ppm 5 ghz band rf receiver specifications bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 66 5 ghz band rf receiver specifications table 17: 5 ghz band receiver rf specifications a a. with minimum rf gain. characteristic condition minimum typical maximum unit cascaded noise figure maximum rx gain ? 4.5 ? db maximum receive level a 5.24 ghz @ 6 mbps ?10 ? ? dbm 5.24 ghz @ 54 mbps ?15 ? ? dbm dc rejection servo loop bandwidth (normal operation) wideband mode ? 500 ? khz narrowband mode 120 hz ? 230 khz adjacent channel power rejection at 20-mhz offset ? tbd ? dbc alternate channel power rejection at 40-mhz offset ? tbd ? dbc minimum rx gain ? ? 15 ? db maximum rx gain ? ? >100 ? db iq amplitude balance ? ? 0.5 ? db iq phase balance ? ? 1.5 ? out-of-band blocking performance without rf band-pass filter (?1 db desensitization): cw 30?4300 mhz ?10 ? ? dbm cw 4300?4800 mhz ?25 ? ? dbm cw 5900?6400 mhz ?25 ? ? dbm table 18: 5 ghz receiver sensitivity parameter condition/notes minimum typical maximum unit frequency range ? 4900 ? 5845 mhz rx sensitivity (10% per for 1000 octet psdu) at external lna input 6 mbps ofdm ?87.5 ?89 ? dbm 9 mbps ofdm ?86.5 ?88 ? dbm 12 mbps ofdm ?86.5 ?88 ? dbm 18 mbps ofdm ?85.5 ?87 ? dbm 24 mbps ofdm ?82.5 ?84 ? dbm 36 mbps ofdm ?79.5 ?81 ? dbm 48 mbps ofdm ?73.5 ?75 ? dbm 54 mbps ofdm ?71.5 ?73 ? dbm rx sensitivity (10% per for 4096 octet psdu) at external lna input a, b a. contact broadcom for details on recommended lnas. b. derate by 1.5 db for -30 c to -10c and 55c to 85c. ht mode mcs 7 (64 qam, r = 5/6, 20 mhz channel spacing) ?69.5 ?71 ? dbm 5 ghz band rf transmitter specifications bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 67 5 ghz band rf transmitter specifications 5 ghz band local oscillat or frequency generator specifications a. reference supported frequencies range from 13 mhz to 52 mhz. table 19: 5 ghz band transmitter rf specifications characteristic condition minimum typical maximu m unit rf output frequency range ? 4920 ? 5805 mhz gain flatness maximum gain ? ? 1 db output ip3 maximum gain ? 35 ? dbm output p1db maximum gain ? 25 ? dbm output power (evm compliant) ? ? ? tbd dbm carrier suppression ? ?15 ? ? dbr ofdm tx spectrum mask (chip output power = 16 dbm) f < fc ? 11 mhz and f > fc + 11 mhz ? ? ?26 dbc f < fc ? 20 mhz and f > fc + 20 mhz ? ? ?35 dbr f < fc ? 30 mhz and f > fc + 30 mhz ? ? ?40 dbr gain control step size ? ? 0.25 ? db/ step i/q baseband 3-db bandwidth ? ? 12 ? mhz amplitude balance dc input ?0.5 ? 0.5 db phase balance dc input ?1.5 ? 1.5 baseband differential input voltage ? ? 0.7 ? vpp tx power ramp up 90% of final power ? ? 2 sec tx power ramp down 10% of final power ? ? 2 sec table 20: 5 ghz band local oscillator frequency generator specifications characteristic condition minimum typical maximum unit vco frequency range ? 4920 ? 5805 mhz reference input frequency range ? ? various a ?mhz reference spurs ? ? ? ?30 dbc local oscillator integrated phase noise (1?300 khz) 4.920?5.700 ghz ? 0.7 ? 5.725?5.805 ghz ? 1.4 ? clock frequency tolerance ? ? ? 20 ppm internal regulator electrical specifications bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 68 section 12: internal regulator electrical specifications core buck regulator (cbuck) caution! functional operation outside the limits specified in this section is not guaranteed. in addition, operating the device under such conditions for an extended period of time can adversely affect the long-term reliability of the device. table 21: core buck regulator (cbuck) specification notes minimum typical maximum units input supply voltage ? 2.7 ? 5.5 v pwm mode switching frequency ? 2.24 2.8 3.36 mhz pwm output current ? ??300ma output voltage range programmable, 25 mv steps 1.0 1.45 1.75 v output voltage accuracy ? ?5?5% pwm ripple voltage, static load ? ? 7 20 mvpp pwm ripple voltage, dynamic load 200 ma, 1 s rise/fall current step ?70100mv burst mode ripple voltage, static <30 ma load current ? ? 80 mvpp pwm mode efficiency 200 ma load current 80 90 ? % burst mode efficiency 10 ma load current 70 80 ? % low power mode efficiency 200 a load current ?60 ?% 5 ma load current ?75 ? quiescent current burst mode ?30 ? a low-power mode ?20 ? power-down ?1? output current limit ? ? 600 ? ma output capacitor must be x5r, rated at > 6.3v 3.76 4.7 5.64 f output inductor see reference schematics and application notes for recommended inductor types. 2.64 3.3 3.96 h start-up time from power-down ? ? 500 1000 s settling time: lpom to burst ensure load current < 5 ma during mode change. ??200 s settling time: burst to pwm mode ensure load current < 30 ma during mode change. ??400 s paldo bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 69 paldo 2.5v ldo (ldo2p5v) table 22: internal paldo a a. paldo has programmable overvoltage protection that can be set to 3.6v or 4.4v: default is enabled. specification notes minimum typical maximum units input supply voltage ? 2.7 ? 5.5 v output current ? ? ? 400 ma output voltage range b b. for psrr performance, the input supply should be at least 200 mv higher than the output. programmable, 100 mv steps 2.7 3.3 4.0 v output voltage accuracy ? ?5 ? 5 % quiescent current no load ? 40 ? a maximum load?8?ma output noise @30 khz, 100 ma ? ? 500 output capacitor (esr: 30m?200 m ) ??3.3? f output current limit ? ? 700 ? ma dropout voltage 400 ma load ? ? 200 mv start-up time from power-down ? ? 30 60 s settling time for voltage step change c c. settling time for v high to low voltage change will depend on load current: tset ~ cout. v / iload. 2.5 to 3.3v(10?90%) ? 20 ? s table 23: 2.5v ldo (ldo2p5v) specification notes minimum typical maximum units input supply voltage ? 2.7 ? 5.5 v output current ? ? ? 50 ma output voltage ? 2.25 2.5 2.75 v quiescent current no load ? 6 ? a max load ?1.5?ma output capacitor (esr: 30 m ?200 m ) ?0.715 f start-up time from power-down ? ? 500 1000 s nv / hz cldo bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 70 cldo table 24: cldo specification notes minimum typical maximum units input supply voltage ? 1.35 1.4 2.0 v output voltage programmable in 25 mv steps 1.10 1.225 1.35 v absolute accuracy ? ? ? 4 % output current ? ? ? 200 ma ldo quiescent current ? ? 10 15 a leakage current through output transistor cldo_pu = 0 ? 0.1 10 a output noise @30 khz, 200-ma load ? 80 ? power supply rejection (psr) @1 khz, 150-mv dropout ? 40 ? db output capacitor output capacitor (esr: 30m?200 m ) ?4.7? f dropout voltage ? 150 ? ? mv start-up time ? ? ? 0.5 ms nv / hz lnldo1, lnldo2 bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 71 lnldo1, lnldo2 table 25: lnldo1 a , lnldo2 a. lnldo1 is only used with lnldoi_vo_sel=0 (1.225v output) to supply sensitive analog blocks: lnldo2s use is not required or recommended. specification notes minimum typical maximum units input supply voltage lnldoi_vo_sel = 0 1.35 1.4 2.0 v lnldoi_vo_sel = 1 3.0 3.3 3.6 output voltage lnldoi_vo_sel = 0 1.10 1.225 1.35 v lnldoi_vo_sel = 1 2.5 2.5 3.1 absolute accuracy ? ??4% output current for lnldo1 ? ??150ma output current for lnldo2 ? ??50ma quiescent current for lnldo1 lnldoi_vo_sel = 0 ?3144 a lnldoi_vo_sel = 1 ? 110 206 quiescent current for lnldo2, 3, 4 lnldoi_vo_sel = 0 ?2942 a lnldoi_vo_sel = 1 ? 108 202 leakage current for lnldo1 lnldo1_pu = 0 ??? a lnldoi_vo_sel = 0 ?0.1 5 lnldoi_vo_sel = 1 ?0.1 9 leakage current for lnldo2, 3, 4 lnldo1_pu = 0 ??? a lnldoi_vo_sel = 0 ?0.1 2 lnldoi_vo_sel = 1 ?0.1 4 output noise @30 khz, 50 ma load lnldoi_vo_sel = 0 ?20 ? lnldoi_vo_sel = 1 ?31 ? psr for lnldo @1 khz, 150 mv dropout ?50 ?db dropout voltage ? 150 ? ? mv start-up time ? ??0.5ms table 26: power management unit specification notes min typ max units total quiescent current from vbat burst mode ? 100 a a. assumes cbuck load current = 0 ua, with paldo, cldo, and lnldos powered down. ?ua low power burst mode ? 50 a ?ua power down ? 11 ? ua input supply voltage ramp-up time 0 to 4.3v 44 ? ? us 4.3 to 5.5v 100 ? ? us nv / hz power-up sequence bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 72 section 13: power-up sequence sdio host timing requirement the sdio host must wait a minimum of 150 ms after the vddc (1.25v dc supply for core) ramps up and settles before initiating access to the bcm4319. for typical designs, one of the bcm4319 internal regulators generates vddc: the regulators are enabled by wl_reg_on going high. reset and regulator control signal sequencing the bcm4319 has two control signals that allow the host to control power consumption by enabling or disabling the wlan and internal regulator blocks. these control signals are as follows: ? wl_reg_on: can be used by a host cpu to power-up or power down the internal bcm4319 regulators. ? ext_por_l: low asserting reset for the wlan core. this pin needs to be driven high or low; it must not be left floating. if ext_por_l is low, the bcm4319 core will be powered off. wl_reg_on and ext_por_l can be tied together. the timing diagram shown in figure 21 on page 73 is provided to indicate proper sequencing of the signals for wlan operation. the timing values indicated are minimum required values; longer delays are also acceptable. note: the timing diagram is not to scale and is only for illustration purposes. reset and regulator control signal sequencing bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 73 figure 21: power-up sequence timing diagram 150 ms 100 ms 25 ms vbat vddio wl_reg_on ext_por_l vbat and vddio present (order is immaterial) > 100 us > 100 us gpio o/p pins z ready to respond to sdio access usb attach strapping values, latched in this window actively driven notes: ext_por_l should be low when vddio is absent. vbat must be either powered on (2.7?5.5v) or off (0v): it cannot be left floating. recommend that wl_reg_on be low when vbat is 0v. wl_reg_on and ext_por_l can be tied together and should be low when either vbat or vddio is low. interface timing specifications bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 74 section 14: interface timing specifications this section describes the interface timing for gspi, sdio (default), and sdio high-speed modes. gspi t iming the gspi host and device always use the rising edge of the clock to sample data. figure 22: gspi timing table 27: gspi timing parameter symbol minimum maximum units note clock period t1 20.8 ? ns f max = 48 mhz clock high/low t2/t3 (0.45 t1) ? t4 (0.55 t1) ? t4 ns ? clock rise/fall time t4/t5 ? 2.5 ns ? input setup time t6 5.0 ? ns setup time, simo valid to spi_clk active edge input hold time t7 5.0 ? ns hold time, spi_clk active edge to simo invalid output setup time t8 5.0 ? ns setup time, somi valid before spi_clk rising output hold time t9 5.0 ? ns hold time, spi_clk active edge to somi invalid csx to clock a ? 7.86 ? ns csx fall to 1st rising edge sdio default mode timing bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 75 sdio default mode timing sdio default mode timing is shown by the combination of figure 23 and table 28 on page 75 . figure 23: sdio bus timing (default mode) clock to csx a ? ? ? ns last falling edge to csx high a. spi_csx remains active for entire duration of spi read/write/write_read transaction (i.e., overall words for multiple word transaction). table 28: sdio bus timing a parameters (default mode) parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) frequency ? data transfer mode fpp 0 ? 25 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 10 ? ? ns clock high time twh 10 ? ? ns clock rise time ttlh ? ? 10 ns clock low time tthl ? ? 10 ns table 27: gspi timing parameter symbol minimum maximum units note t wl t wh f pp t thl t isu t tlh t ih t odly (max) t odly (min) input output sdio_clk sdio high speed mode timing bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 76 sdio high speed mode timing sdio high speed mode timing is shown by the combination of figure 24 and table 29 . figure 24: sdio bus timing (high-speed mode) inputs: cmd, dat (referenced to clk) input setup time tisu5??ns input hold time tih5??ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly 0 ? 14 ns output delay time ? identification mode todly 0 ? 50 ns a. timing is based on cl 40pf load on cmd and data. b. min(vih) = 0.7 vddio_sd and max(vil) = 0.2 vddio_sd. table 28: sdio bus timing a parameters (default mode) (cont.) parameter symbol minimum typical maximum unit t wl t wh f pp t thl t isu t tlh t ih t odly input output 50% vdd t oh sdio_clk sdio high speed mode timing bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 77 table 29: sdio bus timing a parameters (high-speed mode) a. timing is based on cl 40pf load on cmd and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min(vih) = 0.7 vddio_sd and max(vil) = 0.2 vddio_sd. frequency ? data transfer mode fpp 0 ? 50 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl7??ns clock high time twh7??ns clock rise time ttlh??3ns clock low time tthl??3ns inputs: cmd, dat (referenced to clk) input setup time tisu6??ns input hold time tih2??ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly ? ? 14 ns output hold time toh 2.5 ? ? ns total system capacitance (each line) cl ? ? 40 pf usb interface timing specifications bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 78 section 15: usb interface timing specifications usb 2.0 electrical and timing parameters table 30: usb 2.0 electrical and timing parameters parameter symbol condition value unit minimum typical maximum baud rate b ps ??480?mbit/s unit interval ui ? ? 2083 ? ps pll clock generator pll reference clock jitter ? r peak-to-peak jitter input ? ? 10 ps pll output jitter dt f peak-to-peak jitter ? ? 150 ps pll lock time ? ? ? ? 30 s receiver?hs differential input voltage sensitivity v hsdi static | v idp - v idn |300??mv input common mode voltage range v hscm ??50??mv input waveform requirements a rx jitter tolerance a ? hsrx input jitter tolerance ?0.15 0.15 ui input impedance r in single-ended 40.5 45 49.5 squelch detection threshold (differential) v hssq squelch detected ? 100 mv no squelch detected 150 ? mv disconnect detection threshold (differential) v hsdsc disconnect detected 625 ? mv disconnect not detected ? ? 525 mv transmitter?hs output high voltage v hsoh static condition 360 400 440 mv output low voltage v hsol static condition ?10 0 10 mv output waveform requirements a output rise time a t hsr 10 to 90% 500 ? ps output fall time a t hsf 10 to 90% 500 ? ps tx jitter performance a ? hstx tx output jitter ?0.05 ? 0.05 ui output impedance r o single-ended 40.5 45 49.5 chirp-j output voltage (differential) v chirpj hs termination disabled. rpu connected 700 ? 1100 mv usb 2.0 electrical and timing parameters bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 79 chirp-k output voltage (differential) v chirpk hs termination disabled. rpu connected ?900 ? ?500 mv a. see receiver eye diagram template 4 figure 7-16 section 7.1.2.2 of usb 2.0 specifications. table 30: usb 2.0 electrical and timing parameters (cont.) parameter symbol condition value unit minimum typical maximum package information bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 80 section 16: package information package thermal characteristics junction temperature estimation and psi jt versus theta jc package thermal characterization parameter psi-jt ( jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal resistance parameter theta-jc ( jc ). the reason for this is jc assumes that all the power is dissipated through the top surface of the package case. in actual applications, some of the power is dissipated through the bottom and sides of the package. jt takes into account power dissipated through the top, bottom, and sides of the package. the equation for calculating the device junction temperature is as follows: where: ?t j = junction temperature at steady-state condition (c) ?t t = package case top center temperature at steady-state condition (c) ? p = device power dissipation (watts) ? jt = package thermal characteristics; no airflow (c/w) table 31: 138-ball wlbga package thermal characteristics a a. no heat sink, ta = 85oc. this is an estimate based on 2-layer pcb and p = 1.1w. airflow 0 fpm, 0 mps 100 fpm, 0.508 mps 200 fpm, 0.508 mps 400 fpm, 0.508 mps 600 fpm, 0.508 mps ja (c/w) 29.79 27.34 26.59 25.79 25.29 jb (c/w) 1.06???? jc (c/w) 0.09???? jt (c/w) 0.03 0.03 0.03 0.03 0.03 t j t t p jt + = mechanical information bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 81 section 17: mechanical information 138-ball wlbga package figure 25: 138-ball wlbga mechanical information ordering information bcm4319 preliminary data sheet broadcom ? single-chip ieee 802.11? a/b/g/n mac/baseband/radio april 2, 2014 ? 4319-ds05-r page 82 section 18: ordering information table 32: ordering information part number package description ambient temperature bcm4319gkubg 138-ball, wafer-level wlbga package (5.74 mm x 4.53 mm x 0.5 mm, 0.4 mm pitch) single-band 802.11b/g/n 2.4ghz wlan, usb 2.0, sdio ?30 c to 85 c bcm4319xkubg 138-ball, wafer-level wlbga package (5.74 mm x 4.53 mm x 0.5 mm, 0.4 mm pitch) dual-band 802.11a/b/g/n 2.4 ghz and 5 ghz wlan, usb 2.0, sdio ?30 c to 85 c bcm4319skubg 138-ball, wafer-level wlgba package with back side protection (bsp) (5.74 mm x 4.53 mm x 0.5 mm, 0.4 mm pitch) single-band 802.11b/g/n 2.4 ghz wlan usb2.0, sdio ?30 c to 85 c phone: 949-926-5000 fax: 949-926-5203 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 5300 california avenue irvine, ca 92617 ? 2014 by broadcom corporation. all rights reserved. 4319-ds05-r april 2, 2014 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. bcm4319 preliminary data sheet ? |
Price & Availability of BCM4319XKUBGT
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |